EECS 170B
Winter 2014
Due Thursday Week 3
HW 2
DC MOSFET Circuits
(Problem and Figure number refer to 5th Edition S&S)
1.
D4.35 current mirror circuit
Consider the circuit of Fig.E4.12 (as shown below). Let Q1 and Q2 have Vt = 0.6V,
kn=0.2mA/V2, L1 = L2 =
EECS 170B
Winter 2014
Due Tu Week 5
HW 3
Small Signal Operation and Single-stage Amplifier
1. 4.75 DC Operating condition and small-signal voltage gain
For the following circuit, the NMOS transistor has Vtn = 0.9V and VA=50 V and
operates with VD = 2V. Wh
EECS 170
Winter 2014
Due Thursday Week 8
HW 5
1.
A 2-input XOR gate is defined as Y = A +A . A 3-input XOR is defined
B
B
recursively as shown below:
A
B
C
Y
(a) Express Y in terms of A, B and C. Is this an Even parity checker or an
Odd parity checker?
(b
EECS 170LB
Winter 2014
Due Tuesday, Week 4 in Class
Mathematica HW 1
MOSFET Device Modeling using Mathematica
In this simulation lab, we want to incorporate channel length modulation and body effect
into the long channel MOSFET model (posted on class web)
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0 o 51- bd- uad b
o 1 o W m MT w L
VTWKN- LDUU. However PMOS M3 to
O
O X b4. ON {UT an. opwdwamodL
\ 1 O _
HMU' H 5140.415 m b; W.
+0 bow, v J: mmd,
y cam. 19!» WNW/(514$ DP 3 X1 = AE+gC+ZD
aim/w AIB)L 412. [our IL
Mathematica HW 3
Due Thursday Week 10, 3/13/14
RC Ladder Circuit (Revised)
Plot Vc1[t], Vc2[t] and Vc3[t] for the following 3-stage ladder RC network which is used to model the delay for
interconnect in ICs. Use NDSolve (numerical differential equation so
EECS 1703 Lecture Section: Name: So 0 \cm
W2014 Quiz1 (total pts: 15, time: 1hr)
You must circle ALL answers. Partial grading is based on the clarity of your work
I. (15 pts) Consider the following NMOS circuit. Vdd = 5V. Rs = 1 kn. and the NMOSFET has de
EECS 170B
Winter 2014
Do Not Turn in
HW 1
MOSFET I-V Characteristics
(Problem number refer to 5th edition of Sedra & Smith)
1. 4.3 (disparity between NMOS and PMOS)
Knowing that p~0.3n, what must be the relative Ws of NMOS and PMOS if IDS is
to be equal t
Extra-Credit Problem: Charge transfer between 2 capacitor
Consider the circuit shown above. Vc2 and Vc1are initially at 5V and 0V respectively. The switch is closed at t
= 0. Find Vc1(t) and Vc2(t) for t > 0.
The numerical values of C2 and C1 are 10pF and
EECS 170B
W2013
Name:
Quiz 3 (total pts: 25, time: 1hr)
1. Consider an inverter having the following voltage transfer characteristics (VTC ). Find the Noise Margin High
and Noise Margin Low of the inverter from the VTC. Be as accurate as you can. (10 pts)
EECS 170B
W2013
Name:
Quiz 4 (total pts: 25, time: 1hr)
1. (a) Design the logic function Y = +BCD using CMOS via PUN and PDN. (15 pts).
(b) Label W/L next to each transistor in your design in part (a) if we were conform to the basic inverter of
W L n 1.5
EECS 170B
W2013
Lecture Section:
Name:
Quiz1 (total pts: 15, time: 1hr)
1. (25 pts) Consider the following NMOS circuit. Vdd = 5V. The 2 NMOSFETs are identical and have device
parameters: kn = 1 mA V 2 , Vtn = 1V.
(a) Calculate Vout and power dissipated (
EECS 170
Winter 2014
Due Tuesday Week 10
HW 6
PTL circuits
1.
2.
3.
4.
5.
10.49 (PTL) Refer to HW 6a for circuit diagrams
10.51 (PTL)
10.54 (PTL)
10.55 (PTL)
10.56 (PTL)
6. If we 2 NMOS (or for that matter, 2 PMOS) with identical Vtn and kn but different
EECS 170B
Winter 2016
Do Not Turn In
HW 1
MOSFET I-V Characteristics
(Problems can be found in the 5th , 6th ad 7th editions of Sedra & Smith)
1.
Disparity between NMOS and PMOS
Knowing that p~0.3n, and assumes that Ln = Lp (gate length) what must be the
A g Halal) V If A :5 Wk, g 13,13, leaf
0 o 51- — bd- uad b
o 1 o — W m MT “w L
VTWKN- LDUU‘. However PMOS M3 to
O
O X b4. ON {UT an. opwdwamodL
\ 1 O _
HMU' H 5140.415 mﬂ‘ b; W.
+0 bow, v J: mmd,
y cam. 19!» WNW/(514$ DP 3 ’ X1 = AE+gC+ZD
aim/w AIB)L 4’
EECS 1703 Lecture Section: Name: a a "ton
W2015 Quizz (total pts: 15, time: 1hr)
You must circle ALL ansuers. Fania] credit is based on the clarity of your uork.
I. (IS pts) Consider the following NMOS ampliﬁer. The NMOSFEF has device parameters: kn = 2 m
EECS 170B
Winter 2016
Due Th Week 5
HW 3
Small Signal Operation and Single-stage Amplifier
1.
4.75 DC Operating condition and small-signal voltage gain
For the following circuit, the NMOS transistor has Vtn = 0.9V and VA=50 V and
operates with VD = 2V. Wh
Formulae for NMOS and PMOS Devices (last updated: 2/7/17, to be
continuingly updated)
NMOS Baseline Model (=0, no channel modulation effect)
W
kn = kn' : transconductance parameter mA V2
L
kn' = n Cox : process transconductance parameter mA V2
n : chann