EECS 170B
Winter 2016
Do Not Turn In
HW 1
MOSFET I-V Characteristics
(Problems can be found in the 5th , 6th ad 7th editions of Sedra & Smith)
1.
Disparity between NMOS and PMOS
Knowing that p~0.3n, and assumes that Ln = Lp (gate length) what must be the
EECS 1703 Lecture Section: Name: So 0 \cm
W2014 Quiz1 (total pts: 15, time: 1hr)
You must circle ALL answers. Partial grading is based on the clarity of your work
I. (15 pts) Consider the following NMOS circuit. Vdd = 5V. Rs = 1 kn. and the NMOSFET has de
Mathematica HW 3
Due Thursday Week 10, 3/13/14
RC Ladder Circuit (Revised)
Plot Vc1[t], Vc2[t] and Vc3[t] for the following 3-stage ladder RC network which is used to model the delay for
interconnect in ICs. Use NDSolve (numerical differential equation so
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EECS 170LB
Winter 2014
Due Tuesday, Week 4 in Class
Mathematica HW 1
MOSFET Device Modeling using Mathematica
In this simulation lab, we want to incorporate channel length modulation and body effect
into the long channel MOSFET model (posted on class web)
EECS 170
Winter 2014
Due Thursday Week 8
HW 5
1.
A 2-input XOR gate is defined as Y = A +A . A 3-input XOR is defined
B
B
recursively as shown below:
A
B
C
Y
(a) Express Y in terms of A, B and C. Is this an Even parity checker or an
Odd parity checker?
(b
EECS 170B
Winter 2014
Due Tu Week 5
HW 3
Small Signal Operation and Single-stage Amplifier
1. 4.75 DC Operating condition and small-signal voltage gain
For the following circuit, the NMOS transistor has Vtn = 0.9V and VA=50 V and
operates with VD = 2V. Wh
EECS 170
Winter 2014
Due Tuesday Week 10
HW 6
PTL circuits
1.
2.
3.
4.
5.
10.49 (PTL) Refer to HW 6a for circuit diagrams
10.51 (PTL)
10.54 (PTL)
10.55 (PTL)
10.56 (PTL)
6. If we 2 NMOS (or for that matter, 2 PMOS) with identical Vtn and kn but different
Mathematica Hints (updated 1/12/14)
1. Press shift Enter to run the program ie to compute
2. go to Evluation, Abort Evaluation ctrl
. , if not, Quit Kernel to kill a running program
General Reminders
0. Use " Help " to help you
1. All Built in functions s
EECS 170B
Winter 2013
(Do not turn in)
HW 1
MOSFET I-V Characteristics
(Problem number refer to 5th edition of S&S)
1.
4.3 (disparity between NMOS and PMOS)
Knowing that p~0.3n, what must be the relative Ws of NMOS and PMOS if IDS is
to be equal to ISD wh
EECS 170B
Winter 2013
Due Tu Week 7
HW 4
CMOS Inverter (Static & Dynamic Behaviors)
1.
4.105 (part (b) and (c): CMOS Inverter (with revision)
For a digital logic inverter fabricated in a 0.8m CMOS technology for which kn
= 100A/V2, kp = 50A/V2, Vtn = |Vtp
EECS 170B
Winter 2016 (Due Tu Week 7)
HW 4
(Use the ON/OFF model for the diode in all problems)
1. Casting Transistor Amplifier into an Amplifier Model
Consider the following Common Drain amplifier (taken from HW 3, problem 4). We want to
use the Voltage
EECS 170
Winter 2016
Due Thursday Week 9
HW 6
1.
A 2-input XOR gate is defined as
recursively as shown below:
Y A B A B
. A 3-input XOR is defined
A
B
C
Y
(a) Express Y in terms of A, B and C
(b) Implement a 3-input XOR gate using CMOS circuit.
2.
Impleme
EECS 170B
Winter 2016
Due Thursday Week 3
HW 2
DC MOSFET Circuits
(Problems can be found in the 5th , 6th and 7th Editions of S&S)
1.
Current mirror circuit
Consider the circuit of Fig.E4.12 (as shown below). Let Q1 and Q2 have Vt = 0.6V,
kn=0.2mA/V2, L1
EECS 170B
Winter 2016
Due Th Week 5
HW 3
Small Signal Operation and Single-stage Amplifier
1.
4.75 DC Operating condition and small-signal voltage gain
For the following circuit, the NMOS transistor has Vtn = 0.9V and VA=50 V and
operates with VD = 2V. Wh
EECS 1703 Lecture Section: Name: a a "ton
W2015 Quizz (total pts: 15, time: 1hr)
You must circle ALL ansuers. Fania] credit is based on the clarity of your uork.
I. (IS pts) Consider the following NMOS ampliﬁer. The NMOSFEF has device parameters: kn = 2 m
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O
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\ 1 O _
HMU' H 5140.415 mﬂ‘ b; W.
+0 bow, v J: mmd,
y cam. 19!» WNW/(514$ DP 3 ’ X1 = AE+gC+ZD
aim/w AIB)L 4’
EECS 170B
Winter 2012
Due Tu Week 6
HW 4
Small Signal Operation and Single-stage Amplifier
1.
4.75 DC Operating condition and small-signal voltage gain
For the following circuit, the NMOS transistor has Vtn = 0.9V and VA=50 V and
operates with VD = 2V. Wh
EECS 170B
Winter 2012
Due Thursday Week 3
HW 2
DC MOSFET Circuits
1. D4.35 current mirror circuit
Consider the circuit of Fig.E4.12 (as shown below). Let Q1 and Q2 have Vt = 0.6V,
kn=0.2mA/V2, L1 = L2 = 0.8m, W1 = 0.8m and = 0
(a) Find the value of R requ
EECS 170B
Winter 2012
Due Thursday Week 4
HW 3
MOSFET Circuit at DC, MOSFET as Amplifier
1. P 4.43
For each of the following circuits, find the labeled node voltages. For all transistors, kn =
0.4mA/V2, kp = 0.25mA/V2 ,Vnt = 1V, Vtp = -1V and = 0.
5V
5V
5
EECS 170
Winter 2010
Due Thursday Week 9
HW 7
PTL circuits
1.
2.
3.
4.
5.
10.49 (PTL)
10.51 (PTL)
10.54 (PTL)
10.55 (PTL)
10.56 (PTL)
6. If we 2 NMOS (or for that matter, 2 PMOS) with identical Vtn and kn but different
(W/L)1 and (W/L)2 are connected in p
EECS 170B
Winter 2012
Due Th Week 2
HW 1
1. 4.3 (disparity between NMOS and PMOS)
Knowing that p~n, what must be the relative W of NMOS and PMOS if I DS is to be
equal to ISD when operated in saturation mode with the same overdrive voltage.
Explain why n