ECE0132 - Digital Logic
Fall 2015
Homework 1
Due 9/9/2015
Full credit will be given only if you show your work reecting all intermediar
steps that lead you to the nal result.
1. Convert the following numbers from the decimal representation to their corres

University of Pittsburgh
Department of Electrical Engineering
EE/CoE 0132
Homework Assignment #2
Due Date: Tuesday, September 20, 2016
(Late Penalty if turned in after Thursday September 22nd)
1. Exclusive-Or (XOR) is a common logical operator, and is den

University of Pittsburgh
Department of Electrical Engineering
EE/CoE 0132
Homework Assignment #8
Due No Later Than Sunday December 11th
1. Brown & Vranesic 8.2
2. Brown & Vranesic 8.3
3. Brown & Vranesic 8.5
4. Brown & Vranesic 8.6
5. Brown & Vranesic 8.1

University of Pittsburgh
Department of Electrical Engineering
ECE/CoE 0132
Homework Assignment #1
Due Thursday September 8th
(Late Penalty if turned in after 5:00 p.m. , Friday September 9th)
1. Convert the radix-10 number 14510 to the equivalent binary,

University of Pittsburgh
Department of Electrical Engineering
EE/CoE 0132 Spring 2016
Homework Assignment #3
Due In Class, Tuesday, October 4, 2016
(No Late Assignments Accepted Due to 10/6 Exam)
Homework Problems: The following problems are to be complet

University of Pittsburgh
Department of Electrical Engineering
EE/CoE 0132
Homework Assignment #5
Due Thursday, November 10th, 2016
(Late if Received after 11/11)
Quiz on 11/8
Exam #2 on 11/15
1.
2.
3.
4.
5.
6.
7.
Quiz Problems
Brown & Vranesic 6.1
Brown &

University of Pittsburgh
Department of Electrical Engineering
EE/CoE 0132
Homework Assignment #4
Due Tuesday, November 1, 2016
(Late Penalty If Received After Thursday November 3rd, 2016)
1. Brown & Vranesic 4.2
2. Consider the Boolean function f(A,B,C,D)

ECE0132 - Digital Logic
Fall 2015
Homework 3
Due 9/23/2015
1. For the function f (a, b, c) = a b + c + a c
b
(a) Draw the circuit schematic for f in the given form.
(b) Draw the circuit schematic in canonical sum-of-products form. Show the steps of
the ex

ECE0132 - Digital Logic
Fall 2015
Homework 2
Due 9/16/2015
Full credit will be given only if you show your work reecting all intermediar
steps that lead you to the nal results. Identify by name which postulate or
theorem you applied at each step.
1. Prove

ECE 0132
Homework Assignment #1 Solutions
1. Circuit Simulation Applet.
(a) When this circuit is in switch state 101010, the 400 resistor in the upper half of the network is
disconnected from the other components by an open switch, so no current flows thr

EE/COE 0132
Homework Assignment #6 Solutions
1.
The longest path is from inputs m0 and m1 to the output p7.
Propagation through block A involves 1 gate delay in AND gate and two gate delay in FA. Two gate delay
in each of the blocks B, C, D, E, F, G, and

ECE 0132
Homework Assignment #5 Solutions
1. Transmission gate logic circuits.
(a) Inspection of the given circuit reveals that the upper transmission gate will pass its input to its
output when y 0 , and the lower transmission gate will pass its input to

EE/COE 0132
Homework Assignment #3 Solutions
1
Realizations for the function f ( a, b, c ) = ab + bc + ac
a) Circuit schematic in original form.
a
b
f
c
b) Canonical sum-of-products
f (a, b, c) =
=
ab + bc + ac
ab (1) + (1) bc + a (1) c
Identity for AND
=

ECE 0132
Homework Assignment #1 Solutions
1. Circuit Simulation Applet.
(a) When this circuit is in switch state 101010, the 400 resistor in the upper half of the network is
disconnected from the other components by an open switch, so no current flows thr

University of Pittsburgh
Department of Electrical Engineering
6
EE/CoE 0132
Spring 2015
2016
Homework #8
#77 Solutions
1. JK Circuit and Timing Diagram
The logic network for this problem is reproduced below.
X
0
SET
J
1
Q
CLK
Y
K
CLR
Q
From this diagram,