EE 435/535 VERILOG DIGITAL SYSTEMS MODELING
Homework #2
Fall, 2015
Due: 9/17/2015
1. Practice writing the following numbers:
a. Decimal number 123 as a sized 8-bit number in binary. Use _ for readability.
b. A 16-bit hexadecimal unknown number with all x'
EE 435/535 VERILOG DIGITAL SYSTEMS MODELING
Homework #1
Fall, 2015
Due: 9/10/2015
1. Briefly discuss the required design tools and the features of a digital system implemented by
using the following methods:
a) Catalog ICs
b) PLD: CPLD, FPGA
c) ASIC: semi
EE 435/535 VERILOG DIGITAL SYSTEMS MODELING
Homework #4
Fall, 2015
Due: 10/1/2015
This assignment is to turn in the Verilog code for the six checkpoint problems listed in the Active
Learning Session #2 Handout. Please run simulation and turn in the simula
EE 435/535 VERILOG DIGITAL SYSTEMS MODELING
Homework #5
Fall, 2015
Due: 10/8/2015
1. A magnitude comparator checks if one number is greater than or equal to or less than another number. A 4-bit
magnitude comparator takes two 4-bit numbers, A and B, as inp
EE 435/535 VERILOG DIGITAL SYSTEMS MODELING
Homework #3
Fall, 2015
Due: 9/24/2015
1. What are the basic components of a module? Which components are mandatory?
2. A 4-bit parallel shift register has I/O pins as shown in the figure below. Write the module
EE 435/535 VERILOG DIGITAL SYSTEMS MODELING
TERM PROJECT #2
Fall, 2015
Due: 12/10/2015
Design of a Multi-Channel PWM Gernerator
Pulse width modulation (PWM) is a technique which allows the pulse width (duty cycle) and the
pulse period (frequency) of a pul
EE 435/535 VERILOG DIGITAL SYSTEMS MODELING
TERM PROJECT #1
Fall, 2015
Due: 11/5/2015
Design and Implementation of a Binary Integer Sorter
This project is to design a hardware binary integer sorter using Verilog RTL coding. After the
Verilog RTL code has
Chapter 3
Introduction to
Programmable Logic Devices
Types of Programmable Logic Devices (PLDs)
Read Only Memory
Read only memory (ROM) can be used to store truth table or look-up table
(LUT) for implementing logic functions.
The following 8x4 ROM can i
Complex Programmable Logic Devices
and
Field Programmable Gate Array
Reprogrammable Simple PLDs
GAL16V8 (20 Pins)
can have 16 inputs (max) and/or 8 outputs (marcrocells)
has 32 inputs to each of the AND gates (product terms)
GAL22V10 (24 pins)
can have