Fall 2007 Due: 24 September, 2007
Sections A,B,RPY
ECE 3060 Homewo rk 4
VLSI an d Advance d Dig ital Design
Homework should be submitte d in KACB 2350 by 4:30 PM on the due date. 1. Consider a bit slice consisting of a full adder an d a function block. Th
ECE3060: VLSI and Advanced Digital Design
Fall 2007 Homework #1: Solutions
1. Draw the transistor-level schematic of the following binary functions using the minimum number of transistors. Assume that the inputs are available in both true and complemented
Summer 2009
ECE 3060
Prof. David Schimmel Sections A
VLSI and Advanced Digital Design Homework 2 Solution
ECE3060 - Fall a gate 1. We have seen in lecture that the delay of 2005 with input capacitance Cin drivHW # 6 Show that ing a load of Cout is
ECE 3060 VLSI and Advanced Digital Design Homework 3 Solution
September 10, 2002
1. We have seen in lecture that the delay of a gate with input capacitance C in driving a load of C out is d = gh + p = f + p . Show that f = R out C out where R out is the w
Fall 2007 Due: 17 October, 2007
Section A, B, RPY
ECE 3060 Homewo rk 5
VLSI an d Advance d Dig ital Design
Homewo rk should be submitte d at KACB 3318 by 4:30 PM 1. We have seen in lecture that the delay of a gate w ith input capacitance Cin driving a loa
ECE 3060
Advanced Digital Design and VLSI
Test I
June 8, 2007
This exam is close d bo ok close d notes. Calculators are not per mitte d. You may have one sheets of han d written notes. There are four questions. Do read them over before you start to work.
ECE 3060
Advanced Digital Design and VLSI
Sample Test 1
1. Gate Design a) Design an AOI21 Gate. Give the switching function for the pullup (Fsp) and for the pulldown (Fsn) and show the transistor schematic and a gate symbol for this device. b) Suppo
ECE 3060
VLSI and Advanced Digital Design
Lecture 7
Multistage Delay and Logical Effort
Reading Assignment
Chapter 2 of Sutherland, Sproul and Harris
ECE 3060
Lecture 72
Path Effort
The path logical effort is given by
G=
gi
The path electrical effort
ECE 3060
VLSI and Advanced Digital Design
Lecture 9
Logical Effort: Asymmetric Gates, Bundles
More Notation
It turns out, we do not need to x p-fets to be twice as
wide as n-fets (See chapter 7)
Let be dened as the ratio of p-fet width to n-fet
width in
ECE3060 VLSI and Advanced Digital Design, Fall 2012
Homework 3
100 pts.
Assigned January 16
Due prior to 4:15pm on January 24
1. (50) Calculate the worst-case delay for each part. Assume the following:
Rn = Resistance of minimum sized (both min. width and
ECE 3060
VLSI and Advanced Digital Design
Lecture 6
Gate Delay and Logical Effort
ECE 3060
Lecture 61
First Model of Gate Delay
This model will be rened shortly
ECE 3060
Lecture 62
Equivalent R
The average resistance of a
MOSFET is someplace
between the
ECE 3060
VLSI and Advanced Digital Design
Lecture 1
Introduction
You will need:
Text: Modern VLSI Design Wolf
Text: Logical Effort Sutherland et. al.
Reference: Your previous digital design text
Colored pencils
red
green
brown
blue
purple or cyan
To take
ECE 3060
VLSI and Advanced Digital Design
Lecture 3
Fabrication & Design Rules
Reading
Please read chapters 1 and 2 of Wolf
ECE 3060
Lecture 32
Structure of an IC
IC is built on Si substrate
with a number of processes
Wires are fabricated from
metal (A
ECE 3060
VLSI and Advanced Digital Design
Lecture 8
How Many Stages?
Reading Assignment
Chapters 3&4 of Sutherland, Sproul and Harris
(you should have nished Chapters 1&2 by now)
ECE 3060
2
Ideal N depends on
F
We know from the inverter chain example th
ECE 3060
VLSI and Advanced Digital Design
Lecture 10
Two Level Logic Minimization
Motivation
We will study modern techniques for manipulating and
minimizing boolean functions
Issue: Tractibility of minimization problem for large
number of variables
Exa
ECE3060 VLSI and Advanced Digital Design, Spring 2014
Homework 1
100 pts.
Assigned January 7
Due prior to 4:15pm on January 10
1. (15) Find the twos complement representation for the following base 10 numbers (use 10 bits).
a.
b.
3910 =
c.
2.
12510 =
-512
ECE3060, Spring 2004
Final Exam, Section A
ECE3060: VLSI and Advanced Digital Design
Spring 2004, Section A (Prof. Sung Kyu Lim)
Final Exam
April 30, 2004
Guidelines:
1.
2.
3.
4.
5.
6.
Read the questions carefully and pay attention to the special instruct
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ECE 3060
VLSI and Advanced Digital Design
Lecture 16
Technology Mapping/Library Binding
Outline
Modeling and problem analysis
Rule-based systems for library binding
Algorithms for library binding
structural covering/matching
boolean covering/matching
ECE 3060 VLSI and Advanced Digital Design
Lecture 19 Testing
Test Cost
A large percentage (5-40%) of the manufacturing cost of a VLSI chip is due to test Cost is larger for larger circuits
more functionality in a "System-on-a-Chip" means more potential
ECE 3060
VLSI and Advanced Digital Design
Lecture 13
Datapath1: ALUs and Adders
Datapath Floorplan
Busses run through cells
Pitch is matched
Vdd and Gnd are run horizontally
Current draw on Vdd and Gnd is spread in time to minimize spiking
ECE 3060
Da
ECE 3060
VLSI and Advanced Digital Design
Lecture
Datapath2: Registers,Comparators, Shifters, Decoders
D Latch
basic latch
in
out
storing
in
transparent latch
in
out
loading
out
load / store
circuit schematic
ECE 3060
Lecture 162
Single Phase FF (Register
ECE 3060
VLSI and Advanced Digital Design
Lecture 2
MOS Transistor
The pn Junction
Majority carriers diffuse from n to p and from p to n,
leaving trapped impurity (donor) ions behind
Width of depletion region is inversely proportional to
carrier concent
ECE3060: VLSI and Advanced Digital Design
Spring 2006, Section A (Prof. Sung Kyu Lim) Final Exam May 5, 2006
Guidelines: 1. Read the questions carefully. Some problems require MULTIPLE items. 2. Show all your work to receive the full credit. 3. State any
ECE 3060: VLSI and Advanced Digital Design Spring 2006
Midterm #2
30 March 2006 Prof. Vincent Mooneys Section Guidelines: This exam is closed book with no programming of calculators allowed. You may have only two sheets of notes (both the front and the ba
ECE 3060: VLSI and Advanced Digital Design Spring 2006
Midterm #1
16 February 2006 Prof. Vincent Mooneys Section Guidelines: This exam is closed book with no programming of calculators allowed. You may have only one sheet of notes (both the front and the
ECE 3060
VLSI and Advanced Digital Design
Lecture 1
Introduction
You will need:
Text: Modern VLSI Design Wolf
Text: Logical Effort Sutherland et. al.
Reference: Your previous digital design text
Colored pencils
red
green
brown
blue
purple or cyan
To
ECE 3060
VLSI and Advanced Digital Design
Lecture 9
Logical Effort: Asymmetric Gates, Bundles
More Notation
It turns out, we do not need to fix p-fets to be twice as
wide as n-fets (See chapter 7)
Let be defined as the ratio of p-fet width to n-fet
widt
ECE 3060
VLSI and Advanced Digital Design
Lecture 16
Technology Mapping/Library Binding
Technology Mapping/Library Binding
Given an unbound logic network, already
minimized, and a set of library cells
transform into an interconnection of instances
of li
ECE 3060
VLSI and Advanced Digital Design
Lecture 17
Sequential System Design
Setup and Hold Time
Clock
Data
Setup Hold
ECE 3060
Lecture 172
Timing Assertions
A signal is V n (valid n ) if it is stable from before to
after the falling edge of n .
A sign