HW-9
Due Monday April 19, 2004
Name_GT#_
Branches and Jumps
#1. True/False
[ F ] Jump commands (in the MIPS architecture) are always conditional.
[ T ] Branch commands (in the MIPS architecture) are always conditional.
[ T ] Jump commands (in the MIPS arc
ECE2020B HW2 - Due 10 February at 2:07pm.
1) 15 points
Manipulate the following Boolean expression to remove all "big bars"; i.e. only input signals may be inverted.
Y = + + ( + + )
2) 15 points
For the above expression (after your manipulation), draw a m
ECE 2020B Sp16 HW1
Due Monday, January 25, at start of lecture
1)
We use symbols a lot in this class. Connect each symbol to its description.
N-FET (N-channel MOSFET)
P-FET (P-channel MOSFET)
AND gate
OR gate
NOT gate
NAND gate
NOR gate
XOR gate
2
ECE2020: Fundamentals of Digital System Design
Spring 2014, Prof. Sung Kyu Lim
Homework #1: due January 16, 12:05pm
For all problems below, assume that inputs are available in both true and complemented forms. In addition,
do not expand or simplify the or
ECE2020: Fundamentals of Digital System Design
Spring 2014, Prof. Sung Kyu Lim
Homework #2: due January 23, 12:05pm
1. Draw the transistor schematic of the following binary functions using the minimum number of transistors.
Assume that the inputs are avai
ECE2020: Fundamentals of Digital System Design
Spring 2014, Prof. Sung Kyu Lim
Homework #3: due January 30, 12:05pm
1. Use Boolean algebra to derive the sum-of-minterm and product-of-maxterm expressions for the following
binary functions. Do not use truth
ECE2030: Introduction to Computer Engineering
Spring 2014, Prof. Sung Kyu Lim
Homework #4: due Feb 27, 12:05pm
1. Apply the mixed logic method to implement the following functions. Do not simplify the function, and
assume that complemented inputs are not
ECE2030: Introduction to Computer Engineering
Spring 2014, Prof. Sung Kyu Lim
Homework #5: due March 6, 12:05pm
The total point of this homework is 200. When you use combinational building blocks, clearly indicate the
most and least signicant bits for all
ECE2020: Fundamentals of Digital System Design
Spring 2014, Prof. Sung Kyu Lim
Homework #6: due April 8, 12:05pm
1. Consider the following timing diagram, where Q1 and Q2 are the master and slave latch output of a
negative edge-triggered ip-op. Complete t
HW-8 Due March 26, 2004
ECE2030a
Name_
GT# _
Bring this homework to class on Friday March 26.
HW-7. Finite State Machine - Circuit Design
1. Design a synchronous circuit with a two-bit counter (output is C1,C0, negativeedge triggered) that counts the numb
HW-7 Due March 3, 2004
ECE2030a
Name_
HW-7. Finite State Machine - Circuit Design
Design the logic to implement the following FSM. This is the state diagram for a Mealy
machine with 3 states that outputs a "1" on every third "1" received as input, no matt
Name
GT#_
ECE 2 030h, I ntro. T o C omputer E ng., Q UIZ 1
Quiz No. 1: Sept. 13, 2001
Prof. J ohn A . C opeland
School o f E lectrical a nd
C omputer
E ngineering
RULES.
i
This quiz is closed book.
ii.
Non-programmable calculators may be used.
iii
Answer
Name
GT#_
ECE 2030h, Intro. To Computer Eng., QUIZ 2 - Answers
Quiz No. 2: Oct. 18, 2001
Prof. John A. Copeland
School of Electrical and Computer Engineering
RULES.
i
This quiz is closed book.
ii.
Non-programable calculators may be used.
iii
Answer all qu
Name
GT#_
ECE 2030h, Intro. To Computer Eng., QUIZ 3
Quiz No. 3: Nov. 29, 2001
Prof. John A. Copeland
School of Electrical and Computer Engineering
RULES.
i
This quiz is closed book.
ii.
Non-programmable calculators may be used.
iii
Answer all questions a
HW-1 Due Friday Jan. 16
ECE2030a
Name_
Email _
Bring this homework to class on Friday Jan. 16, but do not turn it in until the end of class. Note that A'
is a notation for NOT(A). The symbol "*" is AND, "+" is OR
#1. Fill in the truth table below for the
HW-2
Due Jan. 21, 2004
Name _
GT Email _
Transistor-Level Circuit Understanding
#1. For the following switch level circuit, complete the truth table computed. If a floating or
shorted output is detected, indicate that in the truth table. If no floats or s
Problem Solutions Chapter 2
2-18.*
a)
b)
1
1
1
1
C
1
1
Y
X
c)
Y
1
1
1
W
1
11
X
1
A
1
1
Z
Z
m ( 3, 4, 5, 7, 9, 13, 14, 15 )
m ( 3, 5, 6, 7 )
1
1
1
1
B
1
D
m ( 0, 2, 6, 7, 8, 10, 13, 15 )
2-19*
a) Prime = XZ, WX, XZ, WZ
b) Prime = CD, AC, BD, ABD, BC
Ess
Problem 1. Design an XOR gate (AB' + A'B) using NAND gates and Inverters by the Mixed
Logic Technique. Show the each stage separately. The procedure for performing mixed
logic conversions is as follows:
1. Draw the logic network for the given Boolean equa
HW-6 Due Feb. 21, 2004
ECE2030a
Name_
Bring this homework to class on Monday Feb. 19 for discussion. Turn it in on Friday Feb. 23.
1. Combinatorial Logic - Name the building block that will do the following.
a. A 4-bit number (0-15) input selects one of 1
ECE2020: Fundamentals of Digital System Design
Spring 2014, Prof. Sung Kyu Lim
Homework #7: not due
1. Write a microcode fragment that computes the following register transfer level (RTL) equation.
M [R1] = (M [R3] R4)
M [R2] 25
2
Use the single cycle da