Fall 2007 Due: 24 September, 2007
Sections A,B,RPY
ECE 3060 Homewo rk 4
VLSI an d Advance d Dig ital Design
Homework should be submitte d in KACB 2350 by 4:30 PM on the due date. 1. Consider a bit slice consisting of a full adder an d a function block. Th
ECE3060: VLSI and Advanced Digital Design
Fall 2007 Homework #1: Solutions
1. Draw the transistor-level schematic of the following binary functions using the minimum number of transistors. Assume that the inputs are available in both true and complemented
Summer 2009
ECE 3060
Prof. David Schimmel Sections A
VLSI and Advanced Digital Design Homework 2 Solution
ECE3060 - Fall a gate 1. We have seen in lecture that the delay of 2005 with input capacitance Cin drivHW # 6 Show that ing a load of Cout is
ECE 3060
Advanced Digital Design and VLSI
Test I
June 8, 2007
This exam is close d bo ok close d notes. Calculators are not per mitte d. You may have one sheets of han d written notes. There are four questions. Do read them over before you start to work.
ECE 3060
Advanced Digital Design and VLSI
Sample Test 1
1. Gate Design a) Design an AOI21 Gate. Give the switching function for the pullup (Fsp) and for the pulldown (Fsn) and show the transistor schematic and a gate symbol for this device. b) Suppo
ECE3060: VLSI and Advanced Digital Design
Fall 2006 Homework #9: due October 26, 4:30pm
Solutions
Show all your work to get full credit. 1. Consider the following binary function: F(a; b; c; d) = ad + acd + abcd + bcd + abc. (a) Represent F using the empt
ECE 3060 VLSI and Advanced Digital Design
Lecture 9 Logical Effort: Asymmetric Gates, Bundles
More Notation
It turns out, we do not need to fix p-fets to be twice as wide as n-fets (See chapter 7) Let be defined as the ratio of p-fet width to n-fet width
ECE 3060 VLSI and Advanced Digital Design
Lecture 13 Datapath1: ALUs and Adders
Datapath Floorplan
Busses run through cells Pitch is matched Vdd and Gnd are run horizontally
Current draw on Vdd and Gnd is spread in time to minimize spiking
ECE 3060
Data
ECE 3060 VLSI and Advanced Digital Design
Lecture 1 Introduction
You will need:
Text: Modern VLSI Design Wolf Text: Logical Effort Sutherland et. al. Reference: Your previous digital design text Colored pencils
red green brown blue purple or cyan
To ta
ECE 3060 VLSI and Advanced Digital Design
Lecture 2 MOS Transistor
The pn Junction
Majority carriers diffuse from n to p and from p to n, leaving trapped impurity (donor) ions behind Width of depletion region is inversely proportional to carrier concentr
ECE 3060 VLSI and Advanced Digital Design
Lecture 4 Layout Design & Tools
CMOS Layers
Standard n-Well Process
Active (Diffusion) Polysilicon Metal 1, Metal 2, Metal3 Poly Cut (connects metal 1 to polysilicon) Active Cut (connects metal 1 to active) Via
ECE 3060 VLSI and Advanced Digital Design
Lecture 5 Complex Gates
Example: NAND Gate (Vertical)
ECE 3060
Lecture 52
Example: NAND Gate (Horizontal)
ECE 3060
Lecture 53
Example: NOR Gate (Horizontal)
VDD VDD
OUT OUT
A
B GND
A
B
Other Gates
And Or Invert (
ECE 3060 VLSI and Advanced Digital Design
Lecture 17 Sequential System Design
Setup and Hold Time
Clock Data
Setup Hold
ECE 3060
Lecture 172
Timing Assertions
A signal is V n (valid n ) if it is stable from before to after the falling edge of n . A signa
ECE 3060
VLSI and Advanced Digital Design
Lecture 2
MOS Transistor
The pn Junction
Majority carriers diffuse from n to p and from p to n,
leaving trapped impurity (donor) ions behind
Width of depletion region is inversely proportional to
carrier concent
ECE 3060
VLSI and Advanced Digital Design
Lecture 3
Fabrication & Design Rules
Reading
Please read chapters 1 and 2 of Wolf
ECE 3060
Lecture 32
Structure of an IC
IC is built on Si substrate
with a number of processes
Wires are fabricated from
metal (A
ECE 3060
VLSI and Advanced Digital Design
Lecture 1
Introduction
You will need:
Text: Modern VLSI Design Wolf
Text: Logical Effort Sutherland et. al.
Reference: Your previous digital design text
Colored pencils
red
green
brown
blue
purple or cyan
To take
ECE 3060
VLSI and Advanced Digital Design
Lecture 6
Gate Delay and Logical Effort
ECE 3060
Lecture 61
First Model of Gate Delay
This model will be rened shortly
ECE 3060
Lecture 62
Equivalent R
The average resistance of a
MOSFET is someplace
between the
ECE 3060
VLSI and Advanced Digital Design
Lecture 9
Logical Effort: Asymmetric Gates, Bundles
More Notation
It turns out, we do not need to x p-fets to be twice as
wide as n-fets (See chapter 7)
Let be dened as the ratio of p-fet width to n-fet
width in
ECE 3060 VLSI and Advanced Digital Design
Lecture 6 Gate Delay and Logical Effort
ECE 3060
Lecture 61
First Model of Gate Delay
This model will be refined shortly
ECE 3060
Lecture 62
Equivalent R
The average resistance of a MOSFET is someplace between t
ECE3060: VLSI and Advanced Digital Design
Fall 2006 Homework #7: due Oct 12, 4:30pm, total = 100pts
Solutions
1. Consider the complex gate implementation of F = (a + b)c + d. (a) Draw the stick diagram of F.
-5 incorrect stick diagram
(b) Compute the logi
ECE3060 Homework #8 due Thursday October 19 @ 4:30pm
October 12, 2006 100 points
1. (20) Consider the following function: f = abcd + abcd + abcd + abcd + abcd + abcd + abcd + abcd + abcd. Use your favorite method to derive all possible prime implicants fo
ECE3060: VLSI and Advanced Digital Design
Fall 2006 Homework #10: due November 2, 4:30pm
Use the expression format for answering 1(a), 1(d), and 2(c), e.g., C = ab + c. 1. Consider the following binary function: F (a, b, c, d) = (0, 2, 3, 4, 6, 7, 9, 11,
ECE3060 Homework #11 due Thursday November 16 @ 4:30pm
October 12, 2006 100 points
1. (25) Consider the following function: f = (a+b)(c+d). We want to place f in a standard cell library. Design pattern tree(s) for f using as your base functions NAND and I
ECE3060 Homework#11dueThursdayNovember16@4:30pm
November14,2006 100points
1. (25)Considerthefollowingfunction: f = a b c d .Wewanttoplacefina standardcelllibrary.Designpatterntree(s)forfusingasyourbasefunctionsNANDand INV.Asinthetechnologymappinglecture,u