Spring 2015
ECE 3150
Prof. David Schimmel
Sections A
VLSI and Advanced Digital Design
1. Given the function F = wxz + wxy + wyz + wxz + xyz + wxy + wyz + xyz , write a truth
table for F, and use a K-map to nd a minimum sum of products expression for F.
2.
ECE 3150
Advanced Digital Design and VLSI
Sample Test 1
1. Gate Design
a) Design an AOI21 Gate. Give the switching function for the pullup (Fsp) and for the pulldown
(Fsn) and show the transistor schematic and a gate symbol for this device.
b) Suppose F =
Spring 2015
ECE 3150
VLSI and Advanced Digital Design
Homework 1 Solution
1. Given the function F = wxz + wxy + wyz1 Solutions + wxy + wyz + xyz , write a truth
HW + wxz + xyz
table for F, and use a K-map to nd a minimum sum of products expression for F.
ECE 3150
Prof. David Schimmel
Section A
VLSI and Advanced Digital Design
Homework 2 Solution
1. Design an active high Manchester carry chain circuit at the schematic level.
/P
/G
Cin
Cout
/G
P
/P
2. Again consider an MCC adder. Suppose the delay to comput
ECE 3150
Prof. David Schimmel
Section A
VLSI and Advanced Digital Design
Homework 2
1. Design an active high Manchester carry chain circuit at the schematic level.
2. Again consider an MCC adder. Suppose the delay to compute P and G and their
complements
ECE 3060
Advanced Digital & VLSI
Datapath Designs
1
Datapath Floorplan
Datapath Floorplan
Busses run through cells
Pitch is matched
Vdd and Gnd are run horizontally
Block diagram identies module inputs and
Current
outputsdraw on Vdd and Gnd is spread
ECE 3060
VLSI and Advanced Digital Design
Lecture 6
Gate Delay and Logical Effort
ECE 3060
Lecture 61
First Model of Gate Delay
This model will be rened shortly
ECE 3060
Lecture 62
Equivalent R
The average resistance of a
MOSFET is someplace
between the
VLSI and Advanced
Digital Design
Lecture 4
Gates & Layout
1
Physical Cells
Cells may be gates or networks of gates
Gate cells used in random logic, usually state
machine control
Vertical pitch xed
Vdd and Gnd xed
Network of gates, eg. adder cell used in
d
ECE 3060 VLSI and Advanced Digital Design
Lecture 1 Introduction
You will need:
Text: Modern VLSI Design Wolf Text: Logical Effort Sutherland et. al. Reference: Your previous digital design text Colored pencils
red green brown blue purple or cyan
To ta
VLSI and Advanced
Digital Design
Lecture 2
The MOS Transistor
1
Intrinsic Silicon
Intrinsic silicon is a three dimensional
crystal lattice in which each Si atom covalently shares electrons with each of its
four nearest neighbors
2
n-type Semiconductor
D
ECE 3060 VLSI and Advanced Digital Design
Lecture 7 Multistage Delay and Logical Effort
Reading Assignment
Chapters 1 and 2 of Sutherland, Sproul and Harris
ECE 3060
Lecture 72
Path Effort
The path logical effort is given by G =
gi
The path electrical
Weekly Journal Rubric
Category
Awareness of
Audience &
Expectations
Thoughtful
consideration of
assignment; degree of
self-awareness
Support/Evidence
Use of examples to
support insights and
observations
Coherence
Clear structure
logically moves from
intro