Copy contents of PC into MAR (MAR <- PC);
The PC becomes PC+1. (PC <- PC+1);
Send read signal to the memory (rd);
Copy contents of the memory at MAR into MDR
(MDR <- memory [MAR]);
Copy contents of MDR into IR. (IR<-MDR);
starting address of program
end of program
allocate n words of storage
allocate one word, initialize with value n
allocate n+1 locations,
June 27, 2013
Student #: _
Please turn your communication devices OFF
There are questions on 3 pages.
Write your answers in the spaces provided.
You must answer all 3 question
May 30, 2013
There are questions on 4 pages.
Answer all questions for full points. The points for each part are
shown in square brackets, e.g. 
Show all your work in the spaces provided
Assignment #2: Assembly Language
DUE: Sunday, November 22
Many processors provide instructions to perform various types of shift operations, e.g.
logical shifts, arithmetic shifts and circular shifts. A shift operation
3-Input Majority Function
1 if a majority of the inputs are 1, 0 otherwise
2-level AND-OR implementation
An AND-gate for each row of the table with 1 in the output
Assignment #1: Machine Language
DUE: Sunday, November 08
1) Download the (incomplete) source code for Figure 5.17. Save it as charCount1.bin.
Enter x3000 for the programs load-address on the first line of the program.
Assignment #3: Assembly Language
DUE: Sunday, December 6
Software integer multiplication and division can be implemented using shifting and addition.
Efficient extended multiplication and division algorithms are descri
LC-3 Instruction Set Architecture
Textbook Chapter 5
CMPE12 Summer 2008
Instruction set architecture
What is an instruction set architecture (ISA)?
It is all of the programmer-visible components
and operations of the computer
The ISA provides all the info
Tutorial Week 6 LC3 and Assembly 1
Today we will cover some exercises and
questions regarding assembly and the LC-3.
Keep in mind that these will be useful for
solving the problems you may face while
doing assignment 2!
1) The digits of your ID must not b
Homework 6 Due 12:00PM on Monday, April 9
Primary contact for this homework: Yinggang Huang [email@example.com]
You must do this homework in groups of two. This homework must be submitted online. No hard copies
will be accepted.
4-TO-1 MUX Using (3) 2-TO-1 MUXs
Exercise: Build a 4-TO-1 Multiplexer from three 2-TO-1 Multiplexers.
a) Source the data inputs of each 2-TO-1 MUX
b) Source the final output OUT
c) Source the selector/control in
Patt & Patel, Problem 3.24, Page 89
a. What is the output of the circuit?
When X = 0, S =
When X = 1, S =
b. Modify the circuit (small adjustments only) so that
When X = 0, S = A + B
When X = 1, S = A - B
Figure 3.39, page 89
Operate Instructions (NOT, AND,
Write a single LC-3 machine language instruction:
a) Initialize R0 to 0 (Clear R0)
b) Increment R1
c) Decrement R2
d) Copy from R3 into R4 (like assignment)
e) Left Shift R5
Write LC-3 machine language code fragments:
1. Circuits/Control/Data Path
a. High Bit = (JAMZ * Z) + (JAMN * N) + Next_Address
But, the Next_Address is wired directly to MPC so it doesnt need to be included
b. MPC[0-8] = NEXT_ADDRESS[i] + ( JMPC * MBR[i] )
Typically, we only want the contents
/* Include the standard I/O header file */
/* inGlobal is a global variable because */
/* it is declared outside of all blocks */
/* inLocal, outLocalA, outLocalB are all */
int outLocalA; /* l
1) The enabling mechanism that allows the device to interrupt the processor (Ch. 8)
2) The process that manages the transfer of the I/O data (Ch. 10.2)
I/O Data Transfer
1) Initiate the interrupt
a) Save the state of the interrupted p
Figure 14.4 Page 386
b = Watt(a);
b = Volta(a, b);
int Watt(int a)
w = Volta(w, 10);
int Volta(int q, int r)
General Multiplication Algorithm
Obtain the double-length product of a pair of N-bit unsigned integers.
MPR: Multiplier Register MND: Multiplicand Register ACC: Accumulator Register
The algorithm treats ACC as a high-end extension of MPR
General Division Algorithm
Algorithm is described for N-bit unsigned integers. It assumes a double-length (2N-bit) dividend,
an N-bit divisor and obtains N-bit quotient and remainder.
REM: Accumulator Register QUO: Quotient Register DVR: Divisor Register