Yes. Adding more powerful instructions to the instruction set is a good decision because it provides a
higher performance. Instead of having multiple instructions that theoretically do the same thing and
allocates more memory,
Pipeline: Cycle time determined by slower stage: 350ps
Non-pipelined: Cycle time determined by sum of all stages: 1250ps
LW instruction uses all 5 stages.
Pipelined processor takes 5 cycles at 300ps per cycle for latency of 1500ps.