EEE 333, ASU Fall 2008, Yu (Kevin) Cao Lab #2 Due Thursday, October 9th. The objective of this lab is to practice your VHDL coding and the modeling of combinational logic units. Submission: Demo your results to the TA at least one day before the deadline.
EEE 333: Hardware Design Languages and Programmable Logic
Fall 2008, T Th, 1:30-2:45pm, Engineering Center G G224
Instructor Dr. Yu (Kevin) Cao, GWC 336, ycao@asu.edu Office Hours: T Th, 3:00-4:00pm, GWC 336 TA Ambika Kotthanahalli, akotthan@asu.edu
Cours
EEE 333: VHDL, L-02
CMOS Technology and IC Design
Fall 2008, ASU Yu (Kevin) Cao, yu.cao@asu.edu, GWC 336
Highlight
MOSFET basics
The structure and operation First-order model: a switch + a resistor
CMOS logic: inverter
Logic gate construction Static and
EEE 333: VHDL, L-10
On-Chip Memory
Fall 2008, ASU Yu (Kevin) Cao, yu.cao@asu.edu, GWC 336
Highlight
Memory hardware
Memory architecture SRAM and ROM
VHDL modeling of memory Reading: Chapter 4 in Ashenden's book
Further reading: Chapter 12 in Rabaey's bo
EEE 333: VHDL, L-05
VHDL Basics
Fall 2008, ASU Yu (Kevin) Cao, yu.cao@asu.edu, GWC 336
Highlight
Overview of VHDL VHDL 101
Entity and Architecture Behavioral and Structural elements
Reading: Chapter 1 in Ashenden's book
A good VHDL tutorial is posted at
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Lab #1 No due date. You don't need to turn in anything. The objective of this lab is to help you be familiar with the simulation environment, which is important for other labs during this semester. Tutorial (/usr/loc
WE3D-5
LUMPED ELEMENT EQUIVALENT CIRCUIT PARAMETER EXTRACTION OF DISTRIBUTED MICROWAVE CIRCUITS VIA TLM SIMULATION
Peter Russer', Mario Righi', Channabasappa Eswarappa2 and Wolfgang J.R. Hoefer'
Ferdinand-Braun-Institut Hochstfrequenztechnik Rudower Chaus
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Lab #4 Due Thursday, November 20th. The objective of this lab is to be familiar with on the Spartan-3 FPGA board. Submission: Submit a file with the VHDL code to the digital drop box. You must demonstrate your work t
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Lab #5 Due Thursday, December 4th. The objective of this lab is to practice your FPGA design knowledge. Submission: Submit a file with the VHDL code to the digital drop box. You must demonstrate your work to the TA's
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #1 Due Tuesday, September 16th, 1:30pm, submitted to me in class. The objective of this homework is to practice your knowledge of combinational and sequential logic, as well as the implementation with CMOS g
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #2 Due Thursday, October 9th, 1:30pm, submitted to me in class. The objective of this homework is to exercise your learning of VHDL syntax, basic module definitions and modeling of combinational logic. You c
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #3 Due Tuesday, October 28th, 1:30pm, submitted to me in class. The objective of homework 03 is to practice the VHDL coding of finite state machines. Please review related lectures and book chapters to start
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #4 Data Path with Parity Check
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity parity is generic ( length : integer := 7); port ( clk : in std
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #5 Parity Tree Design
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xor_out is generic ( length : integer := 8); port( rx : in std_logic_vec
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #6 Due Thursday, December 4th, 1:30pm, submitted to me in class. The objective of homework 06 is to practice the logic implementation with FPGA design. Look-Up Table (LUT) The Xactix FPGA company decides to
Chapter 4
How the Laplace transform greatly simplifies system representation and manipulation
4.1
Laplace transform techniques
Many useful techniques depend on the Laplace transform. The Laplace transform of a function f (t) is denoted sometime s by cfw_f
EEE 333, ASU Fall 2008, Yu (Kevin) Cao Lab #3 Due Thursday, November 6th. The objective of this lab is to practice your VHDL coding, memory design, and test schemes. Submission: Demo your results to the TA at least one day before the deadline. Then place