EECS 452 Lecture 38
Today:
Approximations.
Handouts:
printed copy of todays lecture slides,
Read:
cruise the 2nd oor library periodicals.
References:
the web, past experience, whatever.
Please keep the lab clean and organized.
Last one out should close th
EECS 452 Lecture 36
Today:
Some history of radio.
I/Q modulation/demodulation.
Handouts:
Printed copy of todays lecture slides.
FPGA Software Radio article.
Important dates relating to radio.
Read
All about Modulation Part 1, from the web.
www.complextore
EECS 452
Lecture 8
Project proposal
ADC/DAC finish
TI FIR filter
Project proposals
Due at 8pm on Friday (tomorrow)
Template on line
Some discussion about things to cover in slides
from last lecture
Really should meet with me before submitting
proposal
Project proposals
IIR filters,
maybe start on converters
Lecture 8
Project
Project proposals
Template is on-line
Due Friday @8pm
Expect feedback on Sat
Template hits most of
the relevant points
Also be sure to address:
Stretch goals and backoff plan
FIR, IIR filters
Lecture 7
KISSKeep It Simple, the most fundamental
rule of engineering. - Dr. Mark Brehob
FIR vs IIR
FIR vs. IIR (pros)
They can easily be designed to be "linear phase" (and usually
are).
Put simply, linear-phase filters delay the input
DFTs
FIR, IIR filters
Lecture 6
The DFT part of the lecture comes from
Understanding Digital Signal Processing
by Richard Lyons.
KISSKeep It Simple, the most fundamental
rule of engineering. - Dr. Mark Brehob
Many figures in this presentation are from the
EECS 452
Digital Signal Processing Lab
S
F
F
T
T
CX
F
T
F
T
_AND_
Lecture 5
FIR filters: phase and delay
EECS 270 in a lecture:
Logic
Verilog
Handouts:
Lecture notes, slides
Design, in its broadest sense, is the enabler of the digital era its a process
EECS 452
Digital Signal Processing Lab
Lecture 4
FIR filteringjust a bit more
The DFT part of the lecture comes from
DFT
Understanding Digital Signal Processing
by Richard Lyons.
Many figures in this presentation are from the
same book as above.
1
Misc. s
Stuff due
EECS 452
Digital Signal Processing Lab
HW1 due today
Proposal ideas due by midnight tonight
Lecture 3
Direct digital synthesis
FIR filters in C
Follow formatting directions!
Lab 1 and Prelab 2 due at start of lab next
week.
HW2 due on Thu
Notes
EECS 452
Digital Signal Processing Lab
Pre-lab due in lab this week.
It is non-trivial, but not too bad.
Lecture 2
Touch on theoretical basis
Number representation
Direct digital synthesis
Homework due Thursday in class
Project pre-proposal i
EECS 452 Lecture 1
Digital Signal Processing Laboratory
Instructors: Prof. Mingyan Liu (mingyan).
GSI:
Mr. Chih-Wei Wang (wangcw).
Systems (communication, control and signal processing) MDE.
Focus: DSP using TI C5510 DSP microcomputer and Xilinx FPGA.
Tod
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EECS 452, Logic and Verilog Review
Digital logic and Verilog: An In-Class Overview/Review
Say we live in the rather black and white world where things (variables) are either true (T) or false (F).
So if S is Mark is going to the Store and C is Mark likes
Basic Error Detection
Digital logic has applications in any number of places. One of those places is in communication
technology. Most communication devices (your cell phones for example) tend to have communication
errors. In the case of a cell phone, you
EEL 6502 DIGITAL SIGNAL PROCESSING I
Final Exam
Name:
Instructions:
1. Time limit: 1 hr and 30 min.
2. Closed Books and Notes; (Two 8"x11" reference sheets are allowed).
3. Answer any FOUR problems.
4. Return your question paper, answer sheets, and the re
University of South Florida
Assignment # 4
Souad Rochdi
Digital signal processing
Dr Sankar
12/2/2010
Problem 1
Part a
% Problem 1 part a
xi = [1 0 0 0 0 0 0 0];
XI = fft(xi);
subplot(221)
stem(real(XI)
title('Real Part of DFT')
xlabel('Index (xi)')
subpl
EEL 6502 - DIGITAL SIGNAL PROCESSING I
COMPUTER ASSIGNMENT #4 (Due Date: See Course Homepage)
I. DISCRETE FOURIER TRANSFORM
Background Reading: Oppenheim & Schafer: Chapters 8 & 9.
Overview:
The DFT is defined as an operation on an N-point time vector
cfw
EEL 6502 - DIGITAL SIGNAL PROCESSING I
COMPUTER ASSIGNMENT #3 (See Course Homepage)
I. FREQUENCY RESPONSE FOR RATIONAL SYSTEM FUNCTIONS
Background Reading: Oppenheim & Schafer: Section 5.3.
Overview: A simple geometric construction can be used to approxim
EEL 6502 - DIGITAL SIGNAL PROCESSING I
Computer Assignment #2 (due date: See Course Homepage)
I. Basic Sampling Theory
Background Reading: Oppenheim & Schafer: Chapter 4.
Overview: Aliasing and Reconstruction, the two basic principles of sampling can be i
Computer Exercises for Digital Signal Processing
References:
1. Computer Based Exercises for Signal Processing Using MATLAB 5, C. S. Burrus et al.,
Prentice-Hall, 1998. ISBN: 0-13-789009-5
2. Digital Signal Processing Using MATLAB, V. K. Ingle and J. G. P
UNIVERSITY OF SOUTH FLORIDA
MATLAB
Assignment #4
EEL 6502 - Digital Signal Processing I
Mohamad Khawaja
December 3, 2009
Problem 1
Part a
% Problem 1 part a
xi = [1 0 0 0 0 0 0 0];
XI = fft(xi);
subplot(221)
stem(real(XI)
title('Real Part of DFT')
xlabel(
University of South Florida
Assignment # 4
Souad Rochdi
Digital signal processing
Dr Sankar
12/2/2010
Problem 1
Part a
% Problem 1 part a
xi = [1 0 0 0 0 0 0 0];
XI = fft(xi);
subplot(221)
stem(real(XI)
title('Real Part of DFT')
xlabel('Index (xi)')
subpl
UNIVERSITY OF SOUTH FLORIDA
MATLAB
Assignment #3
EEL 6502 - Digital Signal Processing I
Mohamad Khawaja
November 24, 2009
Problem 1
Part a
Log magnitude of the zero:
20log10 1 re j e j = 10log10 1 + r 2 2rcos( )
Log magnitude of the pole:
1
20log10
= 10lo
UNIVERSITY OF SOUTH FLORIDA
MATLAB
Assignment #2
EEL 6502 - Digital Signal Processing I
Mohamad Khawaja
October 29, 2009
Problem 1
Part a(i)
% Problem 1 part a(i)
fsim = 80000;
Tsim = 1/fsim;
fo = 2000;
n = 400;
i = [0:Tsim:(n-1)*Tsim];
x = cos(2*pi*fo*i)
UNIVERSITY OF SOUTH FLORIDA
MATLAB
Assignment #1
EEL 6502 - Digital Signal Processing I
Mohamad Khawaja
October 1, 2009
Problem 1
Part a
% Problem 1 part a
z = 0.9*exp(i*pi)/4);
n = 0:24;
x = z.^n;
%Euler's Identity in the polar form
%Number of samples
%E
Rounding Q numbers.
Lets say we have an 8-bit, Q7, 2s complement number we wish to convert to a 4-bit, Q3, 2s complement
number. First notice that both go from -1 to almost 1, so their range of representation is pretty much the same,
only the resolution i
EECS 452
Midterm review
Project related issues
Do these groups need anything?
Affection EEG group
Digital Symphonic/transcription group
Raspberry Pi:
We are supplying board, USB cable for power, USB hub, HDMI to DVI
cable, 16GB SD card. Also a case (