5/28/15
1
1. Sequential Circuits
Combinational circuits
The outputs are entirely dependent on the current inputs
Contains no storage elements, no feedback, memory-less
Sequential circuits
Consists of a combinational circuit to which storage
elements are

CDA 3201L
Combinational Logic Circuits (I)
Lab 1
Demonstration Due Date: Friday, January 23rd by end of class.
Report Due Date: Sunday, January 25th by 11:59PM.
Part A
Verify that the NAND operation is functionally complete using De Morgans law. (Hint: Sh

GDA 3201 Exam?
Answer the questions in the spaces pmded on the exam. If you run out of "
room for an answer, continue on the back of the page.
Name: LO lw'lLo _. _ ._
1. You have 120 minutes to complete the exam.
2. Exam must be taken in blue or bla

CDA 3201L
Combinational Logic Circuits (I)
Lab 1
Demonstration Due Date: Friday, January 19rd by end of class.
Report Due Date: Sunday, January 21th by 11:59PM.
Part A
Verify that the NAND operation is functionally complete using De Morgans law. (Hint: Sh

CDA 3201L
Combinational Logic Circuits (IV)
Lab 4
Demonstration Due Date: Tuesday, June 9th by end of class.
Report Due Date: Thursday, June 11th by 11:59PM.
Part A
Design a circuit that implements the functions in the following table:
S0 S1
0
0
1
1
0
1
0

CDA 3201L
Combinational Logic Circuits (III)
Lab 3
Demonstration Due Date: Tuesday June 2nd by end of class.
Report Due Date: Thursday, May 4th by 11:59PM.
Part A
Design and wire a circuit to implement the Boolean expression F(x, y, z) = (1, 2, 4, 6, 7) u

CDA 3201L FINAL LAB PROJECT
3-STORY ELEVATOR CONTROLLER
Demonstration Due Date: Wednesday, April 22nd by end of class.
Report Due Date: Friday, April 24th by 11:59PM.
Specifications
Design and implement a finite state machine which controls the operation

CDA 3201
Summer 2015
Homework 1
Complete all of the following problems clearly showing all intermediate steps calculators
with number conversion functions should not be used. A hard copy of your solution must
be turned in at the beginning of class on 5/21

CDA 3201 Computer Logic Design
Homework 2
1. Draw the schematic for the following functions using NOR gates only:
a. ( x y ) z
x y z z ( Idempotenc y Theorem )
x y z z ( Involution Theorem )
x y z z x y z z ( Idempotenc y Theorem )
b. xy xz
x ( y z )

CDA 3201
Summer 2015
Homework 5
Complete all of the following problems clearly showing all intermediate steps. A hard copy
of your solution must be turned in at the beginning of class on 7/14 to receive full credit.
1. [Counter Design] Problem 7.4 from th

CDA 3201L
Combinational Logic Circuits (I)
Lab 1
Demonstration Due Date: friday, Jan 22th by end of class.
Report Due Date: sunday, Jan 24nd by 11:59PM.
Part A
Verify that the NAND operation is functionally complete using De Morgans law. (Hint: Show
that

CDA 3201L
Combinational Logic Circuits (II)
Lab 2
Demonstration Due Date: Wednesday, jan 27th by end of class.
Report Due Date: Friday, jan 29th by 11:59PM.
Part A
Implement the following Boolean expression using only NAND gates. Your implementation
shoul

CDA 3201L
Combinational Logic Circuits (III)
Lab 3
Demonstration Due Date: Friday, feb 5th by end of class.
Report Due Date: Sunday, feb 7th by 11:59PM.
Part A
Design and wire a circuit to implement the Boolean expression F(x, y, z) = (1, 2, 4, 6, 7) usin

CDA 3201L
Combinational Logic Circuits (IV)
Lab 4
Demonstration Due Date: Friday, Feb 12th by end of class.
Report Due Date: Sunday, Feb 14th by 11:59PM.
Part A
Design a circuit that implements the functions in the following table:
S0 S1
0
0
1
1
0
1
0
1
F

CDA 3201 Exam 1 Summer 2315
'I Answer the questions in the spaces provided on the exam. If you run out of.
room for an answer. continue on the back of the page.
Name: =$0LL) TI 0 H S
u#:
. You have 120 minutes to complete the exam.
. Exam must be taken

NAME: _SOLUTIONS_ UNumber:_ Computer Logic Design
Duration: 75 Minutes
CDA 3201
October 1, 2015
Closed Book, Notes, HW
Exam 1
R. Kasturi
One sheet of Letter size paper written on front and back is allowed.
SHOW ALL WORK TO GET PARTIAL CREDIT. MAKE REASONA

CDA 3201L
Sequential Logic Circuits (III)
Lab 7
Demonstration Due Date: Friday, April 3rd by end of class.
Report Due Date: Sunday, April 5th by 11:59PM.
Part A
Design a nine-step counter to count in the following sequence using J-K flip-flops (TTL 7476):

CDA 3201L
Sequential Logic Circuits (I)
Lab 5
Demonstration Due Date: Friday, February 27th by end of class.
Report Due Date: Sunday, March 1st by 11:59PM.
Part A
Verify the operation of a JK flip-flop (TTL 7476) on the breadboard by providing appropriate

CDA 3201L
Sequential Logic Circuits (II)
Lab 6
Demonstration Due Date: Friday, March 20th by end of class.
Report Due Date: Sunday, March 22nd by 11:59PM.
Part A
Design a 4-bit synchronous left-shift register using either D flip-flops (7474) or JK flip-fl

CDA 3201L
Combinational Logic Circuits (II)
Lab 2
Demonstration Due Date: Friday, January 30th by end of class.
Report Due Date: Sunday, February 1st by 11:59PM.
Part A
Implement the following Boolean expression using only NAND gates. Your implementation

CDA 3201L
Combinational Logic Circuits (III)
Lab 3
Demonstration Due Date: Friday, February 6th by end of class.
Report Due Date: Sunday, February 8th by 11:59PM.
Part A
Design and wire a circuit to implement the Boolean expression F(x, y, z) = (1, 2, 4,

CDA 3201L
Combinational Logic Circuits (IV)
Lab 4
Demonstration Due Date: Friday, February 13th by end of class.
Report Due Date: Sunday, February 15th by 11:59PM.
Part A
Design a circuit that implements the functions in the following table:
S0 S1 Functio

CDA 3201L FINAL LAB PROJECT
3-STORY ELEVATOR CONTROLLER
Demonstration Due Date: Friday, April 24th by end of class.
Report Due Date: Sunday, April 26th by 11:59PM.
Specifications
Design and implement a finite state machine which controls the operation of

5/28/15
1
Synchronous Sequential Circuits
1.Analysis of Clocked Sequential Circuits
2.State Reduction and Assignment
3.Design of Synchronous Sequential Circuits
2
Analysis of Clocked Sequential Circuits
The analysis of a sequential circuit consists of ob

CDA 3201L Computer Logic Design Laboratory
Lab Exercise 1
Combinational Logic Circuits ( I )
Part A: Simplify the following Boolean expression using the Laws of Boolean algebra, and implement
the resulting circuit using inverters, 2-input AND gates, and 2