Fall 2012
ECE 2020
Prof. David Schimmel
Section D,E
Digital System Design
Homework 3
1. Draw a CMOS transistor schematic and show both of the gate symbols for implementations of the following functions.
(a)!
(c)!
OAI33
(b)!
2.
AOI222 !
AOI321
(d)!
OAI21
D
CMPE 2020 TEST 3; Open book open notes. S 0 LU Tl ON S
NAME (punt 1n capltal):
GTID#:
Prob 1 (10 points):
The state transition table of a 3state FSM (2 ip ops) is given below. The state AB =
10 is unused. Assume that the machine alway
op reset signal.
3 s
CMPE 2020 Test 2
NAME:
7 GT ID NO:
Open book, open notes, no calculators.
Problem 1 (14 points):
(a) For the complex gate implementation of the function
F = (A+ B) . (C + D) of), draw the pull-up chain below. We assume that
the pull-dn chain has already b
CNIPE 2020 Test 1
(a) Rewrite the function F =(A 0 (B ID 0
C o E using only the OR mction and
inversion. Hint: Use deMorgan s fonnu
1a.
F: WE+D)'C'E
(AFEFD) +2 ~1 E
(b) Draw a circuit for F using
derived in part (a)
A
BDCH-e
only OR gates and in
Finite State Machine Lab
Finite State Machine
Goal: The goal of this experiment is to reinforce state machine concepts by having students design and
implement a state machine using simple chips and a protoboard. This experiment also introduces students
to
HW 5: Due Wed March 4th
1. Prob 6.51 (Wakerly)
Draw the logic diagram for a 16 to 4 encoder using just four 8-input NAND gates.
What are the active levels of the inputs and outputs in your design ?
2. Prob 6.81 (Wakerly)
Write the truth table and a logic
HW 4 ECE 2020 Due 2/20 Friday
1. For each expression below, create a switch level implementation using NFETs and PFETs.
Here you can assume you have the complements of each input. Your design should
contain no shorts or opens. Use as few transistors as yo
HW5 Solutions
1. Prob 6.51 (Wakerly)
Draw the logic diagram for a 16 to 4 encoder using just four 8-input NAND gates.
What are the active levels of the inputs and outputs in your design ?
2. Prob 6.81 (Wakerly)
Write the truth table and a logic diagram fo
State Machine Lab Supplemental Instructions for Using the myDAQ
The board is configured for use without the myDAQ. We will be using the myDAQ since that
allows you to look at intermediate signals for trouble-shooting.
Current configuration
Battery for gro
HW 3: Due Feb 2nd
Problem: Design a gate-level implementation for the following expression using the specified gate
types. Use a mixed-logic design methodology. All gates must have all inputs bubbled or no inputs
bubbled. Cancel all bubble pairs that rema
HW 6 2020 Spring 2015 Due Mon March 9th
Problem 1: Perform the indicated subtraction with the following unsigned binary numbers by taking the
2s complement of the subtrahend.
(a) 11010 10001
(b) 11110 1110
(c) 101001 101
Hint: You need to make the no of b
Datapath Elements
The datapath elements are the functional blocks within a microprocessor that actually interact to
perform computational operations. These tasks include reading/writing to memory, arithmetic, logic
operations, and numerical shift operatio