Chin
Pyon
CSc 4210/6210
COMPUTER ARCHITECTURE
Assignment 2
Fall 2015
Due by: 11:59 PM, September 24, 2015.
1. Design a combinational circuit with 4 binary inputs w, x, y, z, and n binary outputs, A, B, C, .etc,
represented by n bits. A is the most signifi
CSC 4210/6210  Assignment #3
Fall 2004
due Thursday, October 21st
1. [20 points] A digital computer has a common bus system with 8 registers of 16 bytes
each. The bus is constructed with multiplexers. Briefly explain your answers for the
following questi
6.033 Spring 2006, Quiz 1
Page 2 of 13
I Reading Questions
1. [6 points]: Which of the following statements is true for UNIX as described in reading #5
(Ritchie and Thompson. The UNIX timesharing system, Bell System Technical Journal, 57, 6,
part 2, 1978
6.857 Computer and Network Security
Lecture 7
Admin:
Notes from previous semester (only read the section on secret sharing)
Today:
Shamirs secret sharing
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6.033 Spring 2007, Quiz 1
I
Page 2 of 12
Reading Questions
1. [6 points]: Which of the following statements are true of the X Windows System (as described in
the X Windows paper, reading # 5)?
(Circle True or False for each choice.)
A. True / False When a
whats a SAT solver?
what is SAT?
the SAT problem
given a formula made of boolean variables and operators
(P Q) (P R)
nd an assignment to the variables that makes it true
possible assignments, with solutions in green, are:
cfw_P = false, Q = false, R = fal
6.01 Final Exam
Spring 2011
1 Alternative Excitations (8 points)
Find the relation between V1 and V2 that must hold so that I = 1A.
4
3
I
V1
2
V2
Express the relation between V1 and V2 as an equation, and enter the equation in the box below.
equation:
3V1
Goals of Project
To help applied mathematicians in solving
problems
x4
5
2 2
(1 x )
6.871  Lecture 3
1 3
= arcsin( x) tan(arcsin( x) + tan (arcsin( x )
3
3
Symbolic Mathematics: AI
Approaches
Slagle: SAINT
Moses: SIN
Moses and Martin: MACSYMA
ReduceII
M
HW#5
Instructions:
1. The deadline will be the end of this week, i.e., 11:59pm, Mar. 5, 2017
[Problem 1] [points: 5] When S1S0Cin is (111) 2,(110) 2,(101) 2,(100) 2,(011) 2,(001) 2, and (000) 2, what is the
output of Cout D3 D2 D1 D0 respectively? Assumin
HW#1
Instructions:
1. The deadline will be the end of this week, i.e., 11:59pm, Jan 15, 2017.
2. This assignment has two problems. The second problem will be posted after next class. This file
will be updated after posting the second question. Each time I
HW#2
Instructions:
1. The deadline will be the end of this week, i.e., 11:59pm, Jan 29, 2017.
2. This assignment has two problems. The second problem will be posted after next class. This file
will be updated after posting the second question. Each time I
HW#4
Instructions:
1. The deadline will be the end of this week, i.e., 11:59pm, Feb. 19, 2017.
2. This assignment has two problems. The second problem will be posted after next class. This file
will be updated after posting the second question. Each time
12/10/12
The Dawn of Packet Switching
ARPA: 1957, in response to Sputnik
Paul Baran (RAND Corp)
Early 1960s: New approaches for
survivable comms systems; hot potato
routing and decentralized
architecture, paper on packet
switching over digital links
Dona
11/28/12
The Problem
Given: Besteffort network in which
Packets may be lost arbitrarily
Packets may be reordered arbitrarily
Packet delays are variable (queueing)
Packets may even be duplicated
Sender S and receiver R want to communicate reliably
Appl
Sequential Circuits
Combinational logic + storage
Also called as Finite State Machine
Remembers state
Changes output and state based in inputs and current state
Sequenctial Circuits
Inputs
Combinational
Logic Circuit
Storage
Elements
Outputs
Chap. 4 REGISTER TRANSFER AND MICROOPERATIONS
Register Transfer Language
Register Transfer
Bus and Memory Transfers
Arithmetic Microoperations
Logic Microoperations
Shift Microoperations
Arithmetic Logic Shift Unit
Henry Hexmoor
1
SIMPLE DIGITAL SY
Chapter 3
Data representation
1
Twos Complement Notation
The
most used representation for
integers.
All positive numbers begin with 0.
All negative numbers begin with 1.
One representation of zero
i.e.
0 is represented as 0000 using 4bit binary
sequ
Chapter 2
Registers and Memory
An nbit register has a group of n flipflops and some logic
gates and is capable of storing n bits of information.
The flipflops store the information while the gates control
when and how new information is transferred i
Chap 16 Flip Flops
Onebit memory, basic building blocks make memory possible.
Input to load
new state value
Memory
State value
(1 bit)
Two configurations:
Hold (store) = hold onto the state value
Load
= load a new state value
Memory Elements
Memory ele
Chap 15 Combinational Circuits
Output is function of input only
i.e. no feedback
n inputs
Combinational
Circuits
m outputs
When input changes, output may change (after a delay)
Combinational Circuits
Analysis
Given a circuit, find out its function
?
CSc 4210/6210 COMPUTER ARCHITECTURE Fall 2015
Name: Your GSU email: (last 4 digits of your ID):
Ch a Q m a;
l 3 ng COLE l I student._su.edu  32,0
Quiz #3
1 The load input for register; R0, is controlled by the following Boolean conditions
while the sourc
CSc 4210/6210
COMPUTER ARCHITECTURE
Your GSU email:
Name:
Fall 2015
(last 4 digits of your ID):
Solution
@student.gsu.edu
Quiz #2
1. The following state diagram represents a sequential circuit with two T flipflops A and B and one
input x and one output y
CSc 4210/6210
Fall 2015
COMPUTER ARCHITECTURE
Your GSU email:
Name:
(last 4 digits of your ID):
@student.gsu.edu
Quiz #1
1 The following Boolean function is given in sum of products of minterms as follows:
F(x,y,z,w) = m(0,1,3,5,7,9)
a Complete the trut
CSc 4210/6210
COMPUTER ARCHITECTURE
Assignment 1
First name
Fall 2015
Due on September 10, 11:59 pm
Last name
Chin
Pyon
1 Use the truth table to prove that:
i [X`Z + Y`Z +XY+X`Y`]L= [XYZ` + X`Y]L insert your answers in the following table:
(The inserted
Hardware
1. Cpu central processing unit
Arithmetic Logic Unit (ALU) executes arithmetic (addition, subtraction, etc.) and logical
(AND, OR, etc.) operations
Control unit generates a sequence of control signals telling the ALU how to operate; reads
and e
HW#6
Instructions:
1. The deadline will be the beginning of the class next Tuesday, i.e., 02:50pm, Mar. 28, 2017
2. The goal of this HW is to let you get familiar with the instruction set ASAP. So dont complain too
much work.
[Problem 1] [points: 2] Expla
HW#7
[Problem 1] [Points: 5] Write a program loop, using a pointer and a counter, that complement the
contents of hexadecimal locations 500 through 5FF.
[Problem 2] [Points: 5] Write a subroutine to circulate E and AC four times to the right. If AC contai