Data Representation and
Manipulation
Part 3
Bias notation
Let 1111 1111 be the most positive exponent
0000 0000 be the most negative exponent.
Makes sorting easier
Normalized exponent: takes positive binary number represented by exponent
bits and subt
Electronic Circuits
Controlling Flow
to control whether or not current flows into a
circuit, you would use a switch
A) the switch is open no current flows
B) the switch is closed current flows
transistor are voltage-controlled switches
the transistors
Topic 3: Digital Design
Key Ideas
Combinatorial and Sequential Logic
Boolean Algebra
Logic Gates and CMOS Transistors
Basics Digital Components: Multiplexors, Decodes, ROM, SR
Latches, D Latch, D Flip-flops
Finite State Machines
References
H+H Ch 1.
Sequential Circuits
The D Latch
the D input is for data
the C input is for the clock
Q is the state / output
The latch only changes Q
when the clock C=1.
D
x
0
1
Q
Q Latch state (no change)
0 Reset state
1 Set state
D
When C=1, then the state
Q becomes
Finite-State Machines (FSM)
Traffic Light with Yellow Light: Circuits
Because of the dont cares in the last row of the Next State
table, the equation for the Next State for S'2 can be written as
S'2 = S2S1 + S2S1
(i.e. we dont care about S0)
An expressi
Finite-State Machines (FSM)
Overview
a FSM consists of two circuits
1. given current state and input compute the next state
2. given current state (and input) compute the output
Digital Design
CS251 Winter 2016
133
Finite-State Machines (FSM)
Examples of
Building an Adder
Overview
Goal: build a circuit that can add two integers
Key Insight: binary arithmetic can be computed using logic
gates
- Sum = A XOR B
- Carry = A AND B
A
B
Sum
As Binary Sums
0
0
1
+0 +1 +0
0
1
1
Data Representation
As a Truth Tabl
Floating-point Binary Arithmetic
Simple Example
like IEEE 754 format but using 8 bits rather than 32 bits
represent floating-point as (-1)S (1+F) 2E-3
- in the format: S E E E F F F F
- 3 bits for exponent (EEE), 4 for the fraction (FFFF), offset is 3
Topic 5: Single-Cycle Processor Implementation
Key Ideas
Functional Units of a Processor
Fetch-Execute Cycle
Instruction Formats
Control Unit
References
H+H Ch 7.1-7.3
P+H Ch 4.1 to 4.4 and Appendix D.2
Single-Cycle Processor
CS251 Winter 2016
213
A
Edge Triggered vs. Level Triggered
C
Q
C
F0
Level-Triggered (i.e. a D-latch)
0
when C=1, say initially F0 = 1
D
Q
- the 1 will propagate through the NOT
gate, OR gate and D-latch and F0 will become a 0
- the 0 will then propagate through the NOT gate, OR
A Program vs. a Digital Circuit
Executing the Instruction: lw $2, 4($1)
Format of instruction lw $t, i($s) in machine code
i.e. the input to the circuit is
100011
s
t
i
31:26
25:21 20:16
15:0
the opcode is 6 bits, s and t are 5-bits each (enough to spec
Floating Point Numbers
Challenges
How to express very small numbers?
How to express very large numbers?
Solution: scientific notation
-2.34 1023 is normalized
i.e. only a single non-zero digit to the left of the decimal point
0.0002 10-4 not normalize
Data Hazards
NOP Solution
There is a simple way to get rid hazards without additional
hardware have the compiler put in nop (i.e. no operation)
instructions.
e.g.
add $1,$0,$5
add $1,$0,$5
sub $2, $1, $6
nop
nop
sub $2, $1, $6
in MIPS the nop instructio
Digital Design
Review
so far weve seen two type types of electronic components
- CMOS circuits: pMOS and nMOS transistors
- Logic Gates: AND, OR, NOT, NAND, NOR
in this course we typically
- use CMOS circuits to implement logic gates
- use logic gates t
CS 251 Winter 2016
Computer Organization and Design
Instructor: Kevin Lanctot
Acknowledgements and Sources
Much of this material comes from, or is based on, CS251
lecture notes by Stephen Mann and Prabhakar Ragde, with
additional material based on the CS2
Topic 2: Introduction
Key Ideas
Overview of the components of a processor
Assembly Language
Machine Code
Be familiar with these nine MIPS assembly language instructions:
add, sub, addi, subi, lw, sw, beq, bne, slt
References
H+H Ch 6.1 6.4.4
P+H Ch
Single Cycle Architecture
Part 1
Office hours
A) Wed 11:30-1pm
B) Thurs 12-1:30
C) Thursday after class MC 4021 3:50-4:30
Midterm Feb 12 Thursday
Will do some in class review on Thursday (FEB 12)
Covering everything ending at End of Thursday Class
lw
Multi Cycle Architecture
Part 1
Midterm
Piazza
Lecture Material/Slides/ Extra Notes
Assignments and Solutions
Old midterms : good practice
SINGLE CYCLE MATERIAL
FSM: Do not put names of outputs that are false in the states.
BRANCHING
Set On Less Than, slt
Single Cycle Architecture
Part 3
What Statement about memory in the
Datapath is NOT true
A) the instruction and data memory are a type of RAM
B) Data memory can be read from and written to
C) The Registers contain memory in flip flops
D) The Register fil
Multicycle Architecture
Part 2
We wanted you to know about the following event: - Computer Science Upper Year Course Information Session - * Information on all fou
CS Upper Year Information Night
We wanted you to know about the following event:
-Computer
Multi-Cycle /Pipelining
Part 1
Midterm Remarks: A2 marks are up
Midterm Remarks : 1 more week
Check Q5b) (this will not apply to everyone)
Check with Solutions
MULTI CYCLE DATA PATH
STEP 02: DECODE/Register Fetch
STEP 03: Jump
Clock Cycle of Multi-cycl
Pipelining
Part 2/3
Adding in Parallelism to the Datapath
Analogies : Laundry (Wash, Dry, Fold , Put-Away)
OR : Car Manufacturer Assembly Line:
Do We really need to wait for One Instruction to Finish Before We Start a New
Instruction.
If we are to start
Memory
Part 3
If Write Through takes 10cc, and Write Back takes 20cc
Which method would be more efficient for the following code
fragment
A) Write Back
B) Write Through
C) Both are equal
D) None of the above
If Write Through takes 10cc, and Write Back
Memory
Part 2
How Might a cache with
4 words per block be addressed:
A) using byte offset to access the words
B) Using last two bits of address
31, 30 to access words
C) Using bits 2 and 3, next two bits beside
byte offset to select the word
D) doublin
Pipelining
Part 2/3
Midterm Remarks: A2 marks are up
Midterm Remarks : 1 more week
Check Q5b) (this will not apply to everyone)
Check with Solutions
Adding in Parallelism to the Datapath
Analogies : Laundry (Wash, Dry, Fold , Put-Away)
OR : Car Manuf
Memory
Part 2
How Might a cache with
4 words per block be addressed:
A) using byte offset to access the words
B) Using last two bits of address
31, 30 to access words
C) Using bits 2 and 3, next two bits beside
byte offset to select the word
D) doublin
Memory
Part 1
Memory and the Ideal Scenario
Unlimited amount of memory: Programmers Have Illusion that Large amount of Fast
Memory is available.
History Of WWII term paper
Go to the Library get 4 books that cover this topic well
Realize do not have an
cs251
Computer Organization and Design
W15 Rosina Kharal
Course Outline : Webpage
*Consult Hours
*Assignments
*Drop Boxes
Texts
Also on Reserve
DC Library
Clickers
Available at the Bookstore
Class participation marks 5% of grade
Top 75% of all your cli
CS251 Spring 2016
Assignment 05
Due Friday July 15th 10pm
60 Total Marks
Q1.
Pipeline Performance [10 marks]
a. Suppose the SPECINT2020 benchmark suite is executed on a MIPS processor and
returns the following dynamic instruction mix:
25% loads, 15% store
CS251 S16
Assignment 06
DUE July 26th 10pm
45 Total Marks
Q1. (5 marks) Suppose we have a 32-bit MIPS computer with 1 GB of physical memory (main memory).
For virtual memory on this computer, we need to translate a 32-bit virtual address into a 30-bit phy
CS 251 Spring 2016, Assignment 0
1% bonus mark
Friday May 13,
10 PM Submit Using Crowdmark
You may print these pages and write your s olutions i n the s pace provided. Note that you
only need to s ubmit the three pages with questions on them; do not submi
CS251 Spring 2016
Assignment 03
Due Friday June 24th 10pm
55 Total Marks
Q1. Describe the effect that a signal stuck-at-0 fault (i.e., the signal is always 0 regardless of what
it should be) would have for the signals shown below, in the single cycle Data
CS251 S16
*NEW*
Assignment04
Due Tuesday July 05 10pm
50 Total Marks
Q1. (10 marks) This question refers to the pipelined datapath without forwarding and branching is
determined in the MEM stage.
Consider the instructions
100 addi $2, $2, -1
104 beq $3, $