EE 2310 Homework #3 Simple Flip Flops and Timing Diagrams
1. Draw a four-bit synchronous up-counter made out of 74LS74 D flipflops that will count 0000 1111b.
State Table for counter
2. What is the ea
Jonathan Bollinger
Randall Robert
Experiment 10 Traffic Light Controller
There are many applications for controller circuits. One of them is a highway intersection
traffic light. In this experiment yo
Jonathan Bollinger
Randall Robert
Experiment 10 Traffic Light Controller
There are many applications for controller circuits. One of them is a highway intersection
traffic light. In this experiment yo
1
E xperiment 4: R esistor Capacitor Ci rcuits
In t roduction:
The purpose of this lab report is to inform the lab assistant that Ive worked th rough the lab and gained an adequate amount of experienc
1
E xperiment 3: S ilicon Diodes In t roduction:
The purpose of this lab report is to inform the lab assistant that Ive worked th rough the lab and gained an adequate amount of experience in doing so.
Jonathan Bollinger
Randall Robert
Experiment 8 Sequence Detector
Part B:
Design a sequential logic circuit to check an input stream labeled X and to produce an
output Z=1 if the total number of zeros
Experiment 8 Design of Finite State Machines Using
CAD Tools
In this experiment you will be exposed to the coding of FSM Finite State Machines
using Verilog. The procedure will use the methods you wer
Jonathan Bollinger
Randall Robert
Experiment 4 Flip-Flops
Part A:
Construct A SR latch with two NAND gates.
Digital Inputs:
A. Data Inputs S & R from S1 and S2
B. Select Lines None
C. Clock None
Digit
Jonathan Bollinger
Randall Robert
Experiment 3 - Boolean Function Realization Using Decoders and Mulitiplexers
Part A:
Implement a full adder with AND, OR, and NOT gates.
Digital Inputs:
Data Inputs:
Experiment 10 Vending Machine Control
There are many applications for controller circuits. One of them is a vending machine control. In
this experiment you are going to design a sequential logic circu
Digital Logic Lab
EE2731
General Information about the course
Class time & location:
Lecture: 241 Himes, Thursdays 8am-8:50am
Lecturer:
Name: Houman Kamran
Email: [email protected]
Office: EE 322
Office
Digital Logic Lab
EE2731
Quiz 4
To remind you
about positiveedge-triggered D
flip-flop:
Ck
Quiz 4
Extra question for lab report 3
Extra question for lab report 3
A<B
A=B
A>B
A = (1011)2 = (11)10
A = (
Digital Logic Lab
EE2731
module blockingAssignment(
Quiz 7
What value will be in register D:
input A, input B, output C, output D);
input A, input B, output C, output D);
reg C, D;
reg C, D;
initial
i
Digital Logic Lab
EE2731
Quiz 5
Find the correct
correspondences
between X1, X2, X3, X4
and the four definitions
given below
X1 = ?
X2 = ?
X3 = ?
X4 = ?
1)
2)
3)
4)
X1
X2
X3
X4
Time interval when a wa
Digital Logic Lab
EE2731
Quiz 7
Based on the truth table
provided, determine the
values for
X1 = ?
X2 = ?
X3 = ?
X4 = ?
X5 = ?
X6 = ?
X7 = ?
module simple (Clock, a, b, s);
input Clock, a, b;
output s
Experiment 1 - Introduction to the Lab Equipment
The purpose of this experiment is to:
- Introduce you to the lab equipment available for your use.
Each station has the following equipment:
- C.A.D.E.
Digital Logic Lab
EE2731
Upcoming weeks
November 13th to 19th:
Lab session: makeup- session or work on semester project
Lecture session: Ill be in the lab (EE322) for those who
need extra time for m
Digital Logic Lab
EE2731
Quiz 3
Quiz 3
Notes
Midterm has changed to Oct. 13th
Put your partners name on the report (or, even better, each member
of the group submits on his own behalf)
Propagation D
Experiment 4
1. Construct a SR latch with an enable with a single 74LS00, and connect its three inputs S, R and C
to switches S3 , S4 and S5 , and both outputs Q and Q to two logic monitors 3 and 4 so
Experiment 5
Board Using Xilinx ISE Design Suite
Digital Input(s):
A) Data inputs: X, Y, Cin
B) Select lines: None
C) Clock: None
Digital Output(s): Cout, Sum
Truth Table:
Karnaugh Maps: (if any)
Equa
Experiment 8
Design of Finite State Machines Using
CAD Tools
In this experiment you will be exposed to the coding of FSM Finite State Machines using Verilog.
The procedure will use the methods you wer
Digital Logic Lab
EE2731
Upcoming weeks
November 6th to 12th:
Lab session: Experiment 10
Lecture session: solving midterm questions/talk about
semester project
November 13th to 19th:
Lab session: m
Experiment 3
Consider how both arithmetic and logical operations work, as you are designing your 8
bit ALU. Determine how many inputs for data and operation selection you will need. You
should connect
Experiment 4
1. Construct a SR latch with an enable with a single 74LS00, and connect its three inputs S, R and C
to switches S3 , S4 and S5 , and both outputs Q and Q to two logic monitors 3 and 4 so
Experiment 7
Using Language Templates with Xilinx to implement basic
sequential circuits
In experiment 6 you implemented combinational functions using templates for
multiplexers and decoders provided
Experiment 5 Lab Report
Kendall Ravey
Chris Tran
Section 2/Group 8
Experiment 5 - Programming the Digilent Spartan-3E Board Using Xilinx ISE Design Suite
Digital Input(s):
A) Data inputs: a, b, cin
B)
Experiment 2 Electronics
Devin Hull, Chris Tran
2/18/16
Components needed: 9 volt battery with connector, 1 LED, 1 1K resitor.
All components after use must be returned to their boxes.
Light emitting
Lab Report 3
Kendall Ravey
Elizabeth Reiner
Chris Tran
Section 2/ Group 8
Experiment 3 Arithmetic Logic Unit
Digital Input(s):
A) 74LS181
Data inputs : A(3-0), B(3-0)
Data outputs: F7, F6, F5, F4, F3,
Quiz 5 WWW .
Find the correct
correspondences 3V
between X1, X2, x3, x4 OUTPUT TRANSITION A " A " E
and the four definitions
given below 0
.
1) Time interval when a waveform is changing from a logic l
Trevon Brooks
Michael Quaig
Section IDK/ Group IDK
Experiment 2: Programming the Using Xilinx ISE Design Suite
Objective:
Digital Input(s):
A) Data Inputs: X, Y, Cin
B) Select Lines: None
C) Clock:
No
Laboratory Report 4
Kayla Delpit
Jennifer Martin
Section 3/Group 2
Flip-Flops
Construct a 2 SR latches, a D latch by modifying the SR latches, and a master slave
JK flipflop.
SR Latch
Digital Inputs:
Lab 8 Lab Report
Jennifer Martin
Kayla Delpit
Section 3 / Group 2
Counters - create a verilog code that counts up from 0 to 9, then back down from 9 to
0 with an enable that uses LEDs as the output.
D
Lab 9 Lab Report
Jennifer Martin
Kayla Delpit
Section 3 / group 2
Name of the Experiment: Shift registers
Digital Input(s):
A) Data inputs: in1, in2, in3, in4
B) Select lines: None
C) Clock: Clock
Dig
Lab 5- Using Language Templates with Xilinx ISE 14.1
Student name: Kayla Delpit
Student name: Jennifer Martin
Section/group: 3/2
Name of the Experiment: 7 Using Language Templates with Xilinx
ISE 14.1