EE 2740 (Spring 2014)Solution to Homework 5
EE 2740 (Spring 2014)
page 1 of 23
Solution to Homework 5
Version 5: Complete solution. If any changes are made, then the version number will increase.
In the context of timing and delays, we will measure time t
EE 2740 (Spring 2014)Homework 3 (Practice Problems)
EE 2740
1
Homework 3 (Practice Problems)
Version 2: The variables and thier order added (shown in red) in the function of Problem 1b. More problems could be
added later. If any changes are made, then the
EE 2740
Homework 6
Due by 7:30 am on March 26, 2014
Version 0: If any changes are made, then the version number will increase.
Only Problem 7is for credit.
Learning objectives:
Designing combinational circuits with multiplexers
Intuition in combinationa
Logic Circuits
Sections 2.12.4
All figures from the text
Digital Information
EE 2740 (Spring 2014)
2
A Binary Switch
x=0
x=1
(a) Two states of a switch
S
x
(b) Symbol for a switch
Figure 2.1. A binary switch.
EE 2740 (Spring 2014)
3
A Simple Circuit
Figur
EE 2740 (Spring 2014)Solution to Homework 1
EE 2740 (Spring 2014)
page 1 of 8
Solution to Homework 1
Version 0: If any changes are made, then the version number will increase.
1. (Problem 1.3, page 18)
The following rough work shows the repeated division
EE 2740
Homework 5
Due by 7:30 am on March 19, 2014
Version 3: Corrections in Problem 5 in red. If any changes are made, then the version number will increase.
Only Problems 5 and 7 are for credit.
Learning objectives:
Propagation delay of combinational
Flip-Flops and Latches
Chapter 5.1-5.7
All figures from the text
Combinational-Sequential
Combinational
Logic
No feedback
Remembers the
past
Present o/p
depends on
(Spring 2014)
present2and past
Sequential Logic
Feedback
No memory
Present o/p
depends on
E
EE 2740 Homework 3
due Wed., February 24, 2016
1. (a) Convert (243)10 to binary, octal, and hexadecimal.
(b) Convert (00101101)2 into octal, hexadecimal, and decimal.
2. Take the 8-bit 1s complement and the 8-bit 2s complement of each of the following
bin
1
EE 2740 Homework 5
due Wed., March 30, 2016
1. Plot the T input of a positive-edge-triggered T flip-flop that generates the Q output
shown below.
2. Plot the Q and outputs of a basic SR latch given the inputs below. Assume that Q is
initially 1 and is i
EE 2740 HW 5 solutions
1
EE 2740 Homework 5 solutions
Spring 2015
1. Plot the D input of a gated D latch that generates the Q output shown below.
In the solution above, note that, if Q is to be 1 (0) after the next positive clock edge, then
D = 1 (0) befo
EE 2740 HW 1 solutions
1
EE 2740 Homework 1 solutions
Spring 2016
1. Given the following Boolean function:
, , = + + + +
(a) Obtain the truth table of the function.
(b) Draw the logic circuit using the Boolean expression given above.
(c) Simplify the fu
EE 2740 HW 2 solutions
1
EE 2740 Homework 2 solutions
Spring 2016
1. Complete the timing diagram below for the function h(a, b, c) = a(b + c).
2. Use the following function g(x, y, z) = M(0, 1, 4, 5, 7) for parts (a)-(c) below.
(a) Write g as a canonical
EE 2740 HW 2 solutions
EE 2740 Homework 2 solutions
Spring 2015
1. Complete the timing diagram below for the function g(a, b, c) = ab + c.
2. (a) Convert the expression for g(x, y, z) = M(0, 2, 3, 5, 7) from maxterm list form to
minterm list form.
(b) Wri
EE 2740 HW 4 solutions
1
EE 2740 Homework 4 solutions
Spring 2015
1. Construct a truth table to verify that a three-input XOR, that is, , outputs 1 (0)
when the number of 1s in the input is odd (even).
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
0
1
1
0
1
1
EE 2740 HW 1 solutions
1
EE 2740 Homework 1 solutions
Spring 2015
1. Given the following Boolean function:
, , = + + + +
(a) Obtain the truth table of the function.
(b) Draw the logic circuit using the Boolean expression given above.
(c) Simplify the fu
1
EE 2740 Homework 7
due Wed., April 27, 2015
1. The Verilog code is for a sequential circuit with one input, t, and two outputs u and v.
Construct the state table for this circuit.
module prob7_1 (clock, resetn, t, u, v);
input clock, resetn, t;
output r
EE 2740 HW 7 solutions
1
EE 2740 Homework 7 solutions
Spring 2015
1. The state table below is for a Mealy-type circuit with one input, r, and two-bit output
S = s1s0. State A is the reset state. Write Verilog code for this circuit.
present next state outp
EE 2740
Homework 4
Due by 7:30 am on March 7, 2014
Version 1: Some typographic errors (in red) in Problems 5 and 10 have been xed. If any changes are made, then the
version number will increase.
Only Problems 5 and 10 are for credit.
Learning objectives:
Number Representation and
Adders
Section 3.13.4
All figures from the text
Decimal Number
Representation
EE 2740 (Spring 2014)
2
Binary Number
Representation
EE 2740 (Spring 2014)
3
EE 2740 (Spring 2014)
4
Octal System
EE 2740 (Spring 2014)
5
Hexadecimal S
EE 2740 (Spring 2014)Solution to Homework 3 (Practice Problems)
EE 2740 (Spring 2014)
page 1 of 14
Solution to Homework 3 (Practice Problems)
Version 5: Almost complete solution. If any changes are made, then the version number will increase.
1. For the r
EE 2740 (Spring 2014)Solution to Homework 4
EE 2740 (Spring 2014)
page 1 of 13
Solution to Homework 4
Version 3: Complete solution. If any changes are made, then the version number will increase.
1. (Problem 2.38, page 115)
x1 x2
x3
0
00
01
10
0
d
1
1
0
1
EE 2740 (Spring 2014)Solution to Homework 6
EE 2740 (Spring 2014)
page 1 of 13
Solution to Homework 6
Version 2: Solution to all problems except the one bue back included. If any changes are made, then the version number
will increase.
1. (Exercise 4.1, p
EE 2740 Spring 2014
Digital Logic
EE 2740 - Spring 2014
R. Vaidyanathan (Vaidy)
o
o
o
Associate Professor, ECE Dep.
http:/www.ece.lsu.edu/vaidy/home.html
Office hours: MWF 9:40-11:20 am
o
Education:
n
IIT Kharagpur, India: B-Tech and M-Tech
n
Syracuse Uni
EE 2740 Spring 2014
Digital Logic
EE 2740 - Spring 2014
R. Vaidyanathan (Vaidy)
o
o
o
Associate Professor, ECE Dep.
http:/www.ece.lsu.edu/vaidy/home.html
Office hours: MWF 9:40-11:20 am
o
Education:
n
IIT Kharagpur, India: B-Tech and M-Tech
n
Syracuse Uni
Quiz 4
Draw a circuit using 2-input AND gates for finding
the AND of 9 inputs. Try to make the circuit as fast
as possible.
If each gate has a cost of 1 and a delay of 1, what is
the cost and delay of your entire circuit for ANDing
9 inputs?
EE 2740: Marc
Quiz 3
For the following questions show any rough work used.
a) What is the binary representation of 22?
b) Write the 8-bit representation of 22.
c) Write the 8-bit representation of 22 in each of the
following formats.
i. Sign and magnitude representatio
Quiz 2
Draw a circuit equivalent to the one shown
below, that uses only NAND gates.
EE 2740: February 17, 2014
Solution to Quiz 2
With proper insertion of bubbles and using the
fact that NAND , = = , the given
circuit can be transformed as follows.
EE 27
Boolean Algebra
Section 2.5
All figures from the text
Boolean Algebra
George Booles algebraic description of
logical thought and reasoning (1849)
Claude Shannon adopted it for switch
circuits (1937)
Foundation of modern digital technology
EE 2740 (Spring