2.1. The proof is as follows: (x + y ) (x + z ) = xx + xz + xy + y z = x + xz + xy + y z = x(1 + z + y ) + y z
= x 1 + yz = x + yz 2.2. The proof is as follows: (x + y ) (x + y ) = xx + xy + xy + y y = x + xy + xy + 0 = = = 2.3. Proof using Venn
Homework Homework due Wednesday, 01/28 at 7:45AM in class.
1. Determine if the following expression is valid by using a truth table and by using algebraic manipulation: X1X3 + X2X3 + X2X3 = (X1 + X2 + X3)(X1 + X2 + X3)(X1 + X2 + X3) 2. Use algebraic manip
Qa Qb Qc
7.2. The circuit in Figure 7.3 can be modied to implement an SR latch by connecting S to the Data input and S + R to the Load input. Thus the value of S is loaded into the latch whenever either S or R is asserted. Care must
8.1. The expressions for the inputs of the ip-ops are D2 D1 The output equation is = Y2 = w y2 + y 1 y 2 = Y1 = w y1 y2 z = y 1 y2
8.2. The excitation table for JK ip-ops is
Present state y2 y1 00 01 10 11
Flip-op inputs w=0 J2 K2 1d 0d d0 d0 J1
9.1. The next-state and output expressions for the circuit in Figure P9.1 are Y1 Y2 z1 z2 This gives the excitation table = = = = w 1 + y1 y 2 w 2 + y 1 + w1 y2 y1 y2
Present state y2 y1 A B C D 00 01 10 11
Next state w2 w1 = 00 11 11 11 11 01 1
10.1. In the modied shift register the order of the multiplexers that perform the load and enable operations are reversed from the order in Figure 10.4. Bit zero of the modied register is show below.
R0 L E
10.2. (a) A
11.1. Label the wires in the circuit of Figure P11.1 as follows:
a b w3 f d
A complete fault table is
Test w1 w2 w3 000 001 010 011 100 101 110 111
Fault detected a/0 a/1 b/0 b/1 c/0 c/1 d/0 d/1 f /0 f /1
A minimal test set must includ
Homework 1 Solution.
Determine if the following expression is valid by using a truth table and by using algebraic manipulation: x1 x3 + x2 x3 + x2 x3 = x1 + x 2 + x3 x1 + x2 + x3 x1 + x2 + x3
Solving LHS by expanding the product terms
Homework Homework due Wednesday, 02/18 at 7:45AM in class.
Solve the following problems from the Fundamentals of Digital Logic with Verilog Design text. 1. Derive the complete and minimal sums for: a. f = (A,B,C,D)(1,3,7,9,11,12,13,14,15) b. g = (A,B,C,D,
Problem 1 a.
f = AB + CD + BD + AD f = AB + CD + BD
f = AB + A BC + A D E + B D E + BC E + BDE + BC E + BC D + BCD + AC E + AC D + AC E + A B E f = AB + A BC + A D E + BDE + BC D + AC E
Problem 2 a. Distiguished one - cell : 0,9
Analog Versus Digital
Process time varying signals that can take any value across a continuous range of voltages, current or other metric.
Process time varying signals that can take on any value quantized from a continuo
Classification of Digital Circuits
Output depends only on current input values. Output depends on current input values and present state of the circuit, where the present state of the circuit is the current value of the devices memory.
representation of a logical functions truth table. The map for an n-input logic function is an array with 2n cells. Each cell is associated with a minterm.
Two Variable Karnaugh Map
x1 x2 0 0 1 1 0 1 0 1 m0 m1 m2 m3 x2 x1 0 1 0 m0
% Clear screen and variables clc clear all % Initialize variables alpha = 0.12; k = 1;
% Iteration variable
% Note that m1 indicates first run and m2 indicates second run value for % m(k) Ev = 0; % E[v(k)^2] Evv = 0; % E[v(k-1)^2] Ev1 = 0; % E[v(k)