Name
Solution
Computer Organization EE 3755 Midterm Examination
29 October 2001, 12:40-13:30 CST
Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Alias Cant think of a good one. Good Luck!
(16 pts) (16 pts) (20 pts) (16 pts) (16 pts) (16 pts) (
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
Name
Computer Organization
EE 3755
Final Examination
Tuesday, 4 December 2012, 7:309:30 CST
Problem 1
(15 pts)
Problem 2
(15 pts)
Problem 3
(20 pts)
Problem 4
(20 pts)
Problem 5
(5 pts)
Problem 6
(5 pts)
Problem 7
(20 pts)
Exam Total
Alias
Good Luck!
(100
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
LSU EE 3755
Homework 2 Solution
Due: 3 October 2012
Code for the following assignment can be found at
http:/www.ece.lsu.edu/ee3755/2012f/hw02.v.html . Some parts are reproduced here.
Problem 1: Module adder_r4_c3 is a two-level adder similar to cla_12_two
LSU EE 3755
Homework 3 Solution
Due: 15 October 2012
Problem 1: The module below performs subtraction na
vely, using two adders. If the synthesis
program does not see it, the resulting hardware will use the two adders. Re-write the module so
that it uses
LSU EE 3755
Homework 4
Due: 16 November 2012
This assignment is to be completed on the ECE Linux workstations, please follow the instructions at http:/www.ece.lsu.edu/ee3755/proc.html . Accounts will be distributed in class.
Problem 1: Add comments to the
LSU EE 3755
Homework 5 Solution Due: 20 November 2012
For this assignment read Chapter 4 of Patterson & Hennessy, Computer Organization 4th
Edition, up to and including Section 4.4. These sections describe a MIPS implementation which is
most similar to ou
LSU EE 3755
Homework 6 Solution Due: 26 November 2012
This assignment is to be completed on the ECE Linux workstations, please follow the instructions at http:/www.ece.lsu.edu/ee3755/proc.html .
The Verilog code showing the solution is available at http:/
Name
Solution
Computer Organization
EE 3755
Midterm Examination
Wednesday, 24 October 2012,
9:3010:20 CDT
Problem 1
(15 pts)
Problem 2
(14 pts)
Problem 3
(14 pts)
Problem 4
(14 pts)
Problem 5
(18 pts)
Problem 6
(11 pts)
Problem 7
(14 pts)
Exam Total
Alias
Name
Computer Organization
EE 3755
Midterm Examination
Wednesday, 24 October 2012,
9:3010:20 CDT
Problem 1
(15 pts)
Problem 2
(14 pts)
Problem 3
(14 pts)
Problem 4
(14 pts)
Problem 5
(18 pts)
Problem 6
(11 pts)
Problem 7
(14 pts)
Exam Total
Alias
Good Luc
Name
Solution
Computer Organization
EE 3755
Midterm Examination
Wednesday, 24 October 2012,
9:3010:20 CDT
Problem 1
(15 pts)
Problem 2
(14 pts)
Problem 3
(14 pts)
Problem 4
(14 pts)
Problem 5
(18 pts)
Problem 6
(11 pts)
Problem 7
(14 pts)
Exam Total
Alias
LSU EE 3755
Homework 6 Solution Due: 26 November 2012
This assignment is to be completed on the ECE Linux workstations, please follow the instructions at http:/www.ece.lsu.edu/ee3755/proc.html .
The Verilog code showing the solution is available at http:/
LSU EE 3755
Homework 5 Solution Due: 20 November 2012
For this assignment read Chapter 4 of Patterson & Hennessy, Computer Organization 4th
Edition, up to and including Section 4.4. These sections describe a MIPS implementation which is
most similar to ou
LSU EE 3755
Homework 2 Solution
Due: 3 October 2012
Code for the following assignment can be found at
http:/www.ece.lsu.edu/ee3755/2012f/hw02.v.html . Some parts are reproduced here.
Problem 1: Module adder_r4_c3 is a two-level adder similar to cla_12_two
LSU EE 3755
Homework 3 Solution
Due: 15 October 2012
Problem 1: The module below performs subtraction na
vely, using two adders. If the synthesis
program does not see it, the resulting hardware will use the two adders. Re-write the module so
that it uses
Name
Solution
Computer Organization
EE 3755
Final Examination
Tuesday, 4 December 2012, 7:309:30 CST
Problem 1
(15 pts)
Problem 2
(15 pts)
Problem 3
(20 pts)
Problem 4
(20 pts)
Problem 5
(5 pts)
Problem 6
(5 pts)
Problem 7
(20 pts)
Exam Total
Alias Just M
LSU EE 3755
Homework 6 Solution
Due: Not Collected
The following questions are based on the Fall 2012 Final Exam. The rst two questions on that exam
asked about the Hardwired Control (or Multi Cycle) MIPS Implementation. The questions here ask about
the V
LSU EE 3755
Homework 4 Solution
Due: 27 October 2013
Problem 0: Complete this problem as soon as possible. Follow the instructions for Account Setup
and Verilog Homework Workow on http:/www.ece.lsu.edu/ee3755/proc.html.
When the account is set up copy the
Name
Solution
Computer Organization
EE 3755
Midterm Examination
Wednesday, 30 October 2013, 8:309:20 CDT
Problem 1
(21 pts)
Problem 2
(15 pts)
Problem 3
(25 pts)
Problem 4
(11 pts)
Problem 5
(11 pts)
Problem 6
(11 pts)
Problem 7
(6 pts)
Exam Total
Alias T
LSU EE 3755
Homework 4 Solution
Due: 27 October 2013
Problem 0: Complete this problem as soon as possible. Follow the instructions for Account Setup
and Verilog Homework Workow on http:/www.ece.lsu.edu/ee3755/proc.html .
When the account is set up copy th
LSU EE 3755
Problem 1:
Homework 3 Solution
Due: 9 October 2013
A Verilog description of yet another population count module appears below.
module ya_pop(p,a);
parameter N = 256;
input [N-1:0] a;
output
p;
reg [8:0]
p;
integer
i;
always @( a ) begin
p = 0;
LSU EE 3755
Homework 2 Solution Due: 25 September 2013
Read the carry lookahead handout before solving this assignment. It is linked to the course lecture
notes page, http:/www.ece.lsu.edu/ee3755/ln.html .
Problem 1: The handout mentions two types of CGL,
LSU EE 3755
Homework 1 Solution Due: 11 September 2013
Problem 1: Draw a schematic of the logic circuit described by the Verilog code below.
module pie( x, y, a, b, c );
input a, b, c;
wire
t1, t2;
xor
not
and
or
output x, y;
x1(t1,a,b);
n1(x,t1);
a1(t2,x
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
LSU EE 3755
Homework 5 Solution Due: 20 November 2012
For this assignment read Chapter 4 of Patterson & Hennessy, Computer Organization 4th
Edition, up to and including Section 4.4. These sections describe a MIPS implementation which is
most similar to ou
LSU EE 3755
Homework 3 Solution
Due: 15 October 2012
Problem 1: The module below performs subtraction na
vely, using two adders. If the synthesis
program does not see it, the resulting hardware will use the two adders. Re-write the module so
that it uses
LSU EE 3755
Homework 2 Solution
Due: 3 October 2012
Code for the following assignment can be found at
http:/www.ece.lsu.edu/ee3755/2012f/hw02.v.html . Some parts are reproduced here.
Problem 1: Module adder_r4_c3 is a two-level adder similar to cla_12_two
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
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