LSU EE 3755
Homework 1 Solution Due: 11 September 2013
Problem 1: Draw a schematic of the logic circuit described by the Verilog code below.
module pie( x, y, a, b, c );
input a, b, c;
wire
t1, t2;
xor
not
and
or
output x, y;
x1(t1,a,b);
n1(x,t1);
a1(t2,x
: Computer Organization,
,
Chapter Exam
Chapter 3 Arithmetic for Computers
2013/04/30
1. In the IEEE-754 32-bit floating point format, why the exponent field [30-23] is placed in the higher
significant bits than the fraction field [22-0]? (10 Points)
2.
LSU EE 3755
Homework 2 Solution Due: 25 September 2013
Read the carry lookahead handout before solving this assignment. It is linked to the course lecture
notes page, http:/www.ece.lsu.edu/ee3755/ln.html .
Problem 1: The handout mentions two types of CGL,
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
LSU EE 3755
Homework 5 Solution Due: 20 November 2012
For this assignment read Chapter 4 of Patterson & Hennessy, Computer Organization 4th
Edition, up to and including Section 4.4. These sections describe a MIPS implementation which is
most similar to ou
LSU EE 3755
Homework 3 Solution
Due: 15 October 2012
Problem 1: The module below performs subtraction na
vely, using two adders. If the synthesis
program does not see it, the resulting hardware will use the two adders. Re-write the module so
that it uses
LSU EE 3755
Homework 2 Solution
Due: 3 October 2012
Code for the following assignment can be found at
http:/www.ece.lsu.edu/ee3755/2012f/hw02.v.html . Some parts are reproduced here.
Problem 1: Module adder_r4_c3 is a two-level adder similar to cla_12_two
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
LSU EE 3755
Homework 3 Solution
Due: 15 October 2012
Problem 1: The module below performs subtraction na
vely, using two adders. If the synthesis
program does not see it, the resulting hardware will use the two adders. Re-write the module so
that it uses
LSU EE 3755
Homework 2 Solution
Due: 3 October 2012
Code for the following assignment can be found at
http:/www.ece.lsu.edu/ee3755/2012f/hw02.v.html . Some parts are reproduced here.
Problem 1: Module adder_r4_c3 is a two-level adder similar to cla_12_two
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
Name
Computer Organization
EE 3755
Final Examination
Tuesday, 4 December 2012, 7:309:30 CST
Problem 1
(15 pts)
Problem 2
(15 pts)
Problem 3
(20 pts)
Problem 4
(20 pts)
Problem 5
(5 pts)
Problem 6
(5 pts)
Problem 7
(20 pts)
Exam Total
Alias
Good Luck!
(100
LSU EE 3755
Problem 1:
Homework 1 Solution Due: 10 September 2012
Draw a schematic of the logic circuit described by the Verilog code below.
module pie(x,a,b,c);
input a, b, c;
wire
t1, nc;
and a1(t1,a,b);
not n1(nc,c);
or o1(x,t1,nc);
endmodule
a
b
outpu
LSU EE 3755
Homework 2 Solution
Due: 3 October 2012
Code for the following assignment can be found at
http:/www.ece.lsu.edu/ee3755/2012f/hw02.v.html . Some parts are reproduced here.
Problem 1: Module adder_r4_c3 is a two-level adder similar to cla_12_two
LSU EE 3755
Homework 3 Solution
Due: 15 October 2012
Problem 1: The module below performs subtraction na
vely, using two adders. If the synthesis
program does not see it, the resulting hardware will use the two adders. Re-write the module so
that it uses
LSU EE 3755
Homework 4
Due: 16 November 2012
This assignment is to be completed on the ECE Linux workstations, please follow the instructions at http:/www.ece.lsu.edu/ee3755/proc.html . Accounts will be distributed in class.
Problem 1: Add comments to the
LSU EE 3755
Homework 5 Solution Due: 20 November 2012
For this assignment read Chapter 4 of Patterson & Hennessy, Computer Organization 4th
Edition, up to and including Section 4.4. These sections describe a MIPS implementation which is
most similar to ou
LSU EE 3755
Problem 1:
Homework 3 Solution
Due: 9 October 2013
A Verilog description of yet another population count module appears below.
module ya_pop(p,a);
parameter N = 256;
input [N-1:0] a;
output
p;
reg [8:0]
p;
integer
i;
always @( a ) begin
p = 0;
LSU EE 3755
Homework 4 Solution
Due: 27 October 2013
Problem 0: Complete this problem as soon as possible. Follow the instructions for Account Setup
and Verilog Homework Workow on http:/www.ece.lsu.edu/ee3755/proc.html .
When the account is set up copy th
: Computer Organization,
,
Chapter Exam
Chapter 3 Arithmetic for Computers
2013/04/30
1. In the IEEE-754 32-bit floating point format, why the exponent field [30-23] is placed in the higher
significant bits than the fraction field [22-0]? (10 Points)
2.
: Computer Organization,
,
Chapter Exam
Chapter 5.1~5.4-Large and Fast: Exploiting Memory Hierarchy
2013/06/18
1. The basic concept of cache take advantage of temporal and spatial locality in the execution of
application program. Show a short segment of
: Computer Organization,
,
Chapter Exam
Chapter 4-The Processor
2013/06/04
1. Please answer the following questions.
(1) Whats challenge in implementation of single cycle to pipeline? (5%)
(2) Pipelining can decreases the execution latency of instruction
: Computer Organization,
,
Chapter Exam
Chapter 4-1 ~ 4-4 The Processor
2013/05/14
1.
Please draw the single cycle datapath of load instruction. (20%)
2.
Please draw the single cycle datapath of add instruction (20%)
3.
Given the datapath of a single-cyc
: Computer Organization,
,
Chapter Exam
Chapter 1-Computer Abstractions and Technology
2013/03/26
1. How to improve CPU performance under same Instruction Set Architecture following three ways:
i.
Clock rate improvement
ii.
Reduce CPI
iii.
Reduce instruc
: Computer Organization,
,
Chapter Exam
Chapter 2-instructions:language of the computer
2013/04/30
1.
This diagram is base addressing format of MIPS.
Please draw similar diagrams for the following MIPS addressing modes. (40%)
a. Immediate addressing
b. R
:
Design a sequence detector to detect a sequence of three or more
consecutive 1's in a string of bits coming through an input line.
:
2016/12/12
:
B043040001
:
sequence detector
/D flip-flop
module D_flip_flop(
output Q,
input D, Clk, reset
);
reg
Operating Systems, Spring 2014
Midterm
2:10pm 3:50pm, Tuesday, April 22, 2014
I NSTRUCTIONS :
1. This is a closed-book exam.
2. Try to solve all of the problems.
3. Try to give short answers. (Hint: An answer need not always be longer than the question.)
Operating Systems, Spring 2013
Midterm
2:10pm 3:50pm, Tuesday, April 23, 2013
I NSTRUCTIONS :
1. This is a closed-book exam.
2. Try to solve all of the problems.
3. Try to give short answers. (Hint: An answer need not always be longer than the question.)
:ComputerOrganization,
,
Chapter Exam
Chapter 3 Arithmetic for Computers
2013/04/30
1. The following table shows pairs of decimal numbers.
A
B
0
128
(1) Assume A and B are signed 8-bit decimal integers. Calculate A + B. Is there overflow, underflow,
or
Name
Solution
Computer Organization EE 3755 Midterm Examination
29 October 2001, 12:40-13:30 CST
Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Alias Cant think of a good one. Good Luck!
(16 pts) (16 pts) (20 pts) (16 pts) (16 pts) (16 pts) (