COE/EE 243
Digital Logic
Session 37; Page 1/3
Spring 2003
EE/CompE 243
Additional State Machine Design Examples
1. Design a Moore machine state diagram for a sequence detector that outputs a 1 after receiving a
sequence with at least one 1 and three 0s in

NEW DISCOVER FOR FSM (OVERLAPING)!
Let see first example!
101 Detector
Step 1: Identify the number for each bit.
1st bit = > 1
2nd bit => 0
3rd bit => 1
Step 2: Create a draft state table.
State
Current Sequence
X=0
X=1
Step 3: List out all possible curre

Laboratory Exercise 6
Adders, Subtractors, and Multipliers
The purpose of this exercise is to examine arithmetic circuits that add, subtract, and multiply numbers. Each
type of circuit will be implemented in two ways: rst by writing VHDL code that describ

Laboratory Exercise 2
Numbers and Displays
This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion
and binary-coded-decimal (BCD) addition.
Part I
We wish to display on the 7-segment displays HEX3 to HE

Laboratory Exercise 4
Counters
This is an exercise in using counters.
Part I
Consider the circuit in Figure 1. It is a 4-bit synchronous counter which uses four T-type ip-ops. The counter
increments its count on each positive edge of the clock if the Enab

Laboratory Exercise 5
Clocks and Timers
This is an exercise in implementing and using a real-time clock.
Part I
Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX20. Derive
a control signal, from the 50-MHz

DE1 Development and Education Board
Thank you for using the Altera DE1 Development and Education board.
The purpose of this board is to provide the ideal vehicle for learning about digital logic, computer organization,
and FPGAs. It uses the state-of-the-

Getting Started with Alteras DE1 Board
This document describes the scope of Alteras DE1 Development and Education Board and the suporting
materials provided by the Altera Corporation. It also explains the installation process needed to use a DE1
board con

1. Draw state diagram of Mealy and Moore machines
for a sequence detector system which the outputs a
1 when exactly two of the last three inputs are 1.
2. What is the sequence that needs to be detected by the
system? Moore or Mealy?
0
Reset
A
[0]
1
0
B
[0

ECE 331 Digital System Design
Derivation of State Graphs and State Tables
(Lecture #21)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from

Finite State Machines
By Mike Chen
Finite State Machines
vs.
Combinational Logic Units
Combinational logic units are a type of
logic circuit whose output is a pure
function of the present input only.
Finite State Machines, used in sequential
logic, have

Mealy state machine
In the theory of computation, a Mealy machine is a finite state transducer that
generates an output based on its current state and input. This means that the state
diagram will include both an input and output signal for each transitio

CHAPTER
,
12
Media Access
Control (MAC)
W
hen nodes or stations are connected and use a common link, called a multipoint or
broadcast link, we need a multiple-access protocol to coordinate access to the link.
The problem of controlling the access to the m