ECE52 Spring 11 Lecture 19
2/25/11
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In binary: IEEE Standard Floating Point Format
32 bits S Sign 0 denotes + 1 denotes E 8-bit excess-127 exponent M 23 bits of mantissa
(a) Single precision
64 bits S Sign E 11-bit excess-1023 exponent M 52 bits of manti
ECE52 Spring 11 Lecture 18
2/23/11 Go Beavers! 310 game conference losing streak shattered! 2/3 of the team M.E. or CompSci.
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The real magic comes from using cascaded levels of lookahead!
Build basic blocks of size k bits, then use second level of looka
ECE52 Spring 11 Lecture 17
2/21/11 Lab this week: ADC Lunch: Wednesday, noon-1ish, LSRC
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1's, 2's complement - examples
63-27: What is minimum number of bits this calculation can be conducted in?
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1's, 2's complement - examples
63-27: What is minimum
ECE52 Spring 11 Lecture 15
2/16/11
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Signed numbers
Need a way to represent positive and negative integers. Three different systems have been developed; all have their uses
Sign-magnitude representation 1's complement representation 2's complement repre
ECE52 Spring 11 Lecture 14
2/14/11 Watson vs Humans? Digilunch Wednesday noon LSRC
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Base 2
B = bn-1bn-2.b1b0
V ( B ) = bn -1 2 n -1 + bn - 2 2 n - 2 + . + b1 21 + b0 20 = bi 2i
i =0 n -1
So n-bit number can represent numbers from 0 to 2n- 1 Left-most bit
ECE52 Spring 11 Lecture 12
2/9/11 75 minute class No class 2/11/11 Midterm 2/18/11
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Espresso your logic minimization friend
Your book eventually gets around to mentioning espresso briefly near the end of chapter 4 espresso is an algorithm from UC Berkel
ECE52 Spring 11 Lecture 20
2/28/11
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Memory element zoo
S - R edge sensitive Latch J - K level sensitive non - gated D Flip - flop T
plus SRAM/DRAM cells
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Gated SR latch
again assuming no propagation delay. first use of "clk" as our enable suggesting ho
ECE52 Spring 11 Lecture 21
3/2/11 Exam Schedule: Thursday 9-12
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What will we build with these things?
Registers and other memory Counters Finite state machines!
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Electronic lock (sequence recognizer)
want a circuit with 3 buttons that recognizes patte
ECE52 Spring 11 Lecture 22
3/4/11 Spring Break follows
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One more design example (from MIT OpenCourseware needed in lock and vending machine!)
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Finite State Machine M=cfw_S,X,Y,
A finite, nonempty set S=cfw_si of states
|S| <= 2n for n
ECE 52 Midterm Examination I
This is an in-class, closed-book, closed-notes, no-calculator, no-cellphone exam. You may consult a 1page exam sheet that you have prepared for reference prior to the exam. You will have 80 minutes.
Please answer all questions
ECE 52 Midterm Examination I
This is an in-class, closed-book, closed-notes, no-calculator exam. You may consult a
1-page information sheet that you have prepared for reference prior to the exam. You
will have 80 minutes. Please answer all questions.
Plea
ECE 52 Midterm Examination I
This is an in-class, closed-book, closed-notes, no-calculator, no-cellphone exam. You may consult a 1page information sheet that you have prepared for reference prior to the exam. You will have 80
minutes. Please answer all qu
70pts Total
ECE 52 Midterm Examination I
This is an in-class, closed-book, closed-notes, no-calculator exam. You may consult a
1-page information sheet that you have prepared for reference prior to the exam. You
will have 80 minutes. Please answer all que
ECE151
Midterm 2
NAME:_
Please answer all questions in the space available or on attached sheets. If you attach any extra sheets be sure your name is on each page. You may consult one page of notes about combinational logic, and one page of notes about se
ECE 52 Midterm Examination II
This is an in-class, closed-book, closed-notes, no-calculator exam. You may consult the 2-page information sheet that you have prepared for reference prior to the exam. You have 80 minutes.
Please print your name and sign thi
Wolter & Ybarra
Duke University Department of Electrical and Computer Engineering ECE 27 Spring 2011 Homework 4 (Due Wednesday, February 16)
All problems must be solved completely in terms of the symbols given before numbers are inserted. Problems not s
ECE52 Spring 11 Lecture 9
2/2/11
1
Additional digital design building blocks
Non-inverting buffer Tri-state buffers Transmission gates Book introduces the last two backwards.!
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Non-inverting buffer
For either high capacitive load or high current requir
ECE52 Spring 11 Lecture 8
1/31/11 MIDTERM 1 IN CLASS 2/18/11 Closed Book; 1 sheet (1 side) of notes
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PAL-like block (details not shown)
PAL-like block
D Q
D Q
D Q
Figure 3.33. A section of the CPLD in Figure 3.32.
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Compatible chip still available at Di
ECE52 Spring 11 Lecture 35
4/11/11 Interim project progress reports due Friday 4/15/11 Viewed some of http:/aturingmachine.com/ in class
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A FSM with infinite memory: Turing Machines
Consider a system consisting of Finite State Machine M which is coupled
ECE52 Spring 13 Lecture 33
4/6/11 Protocomputer: Subroutines Midterm 2: Friday 4/8/11
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Subroutine behavior
What if we just had "GOTO": Given SQRT subroutine called from multiple places 000 <Program begins> . 109 READ X ; ACX 110 GOTO SQRT ; Always opera
ECE52 Spring 11 Lecture 29
3/28/11 Midterm 2 4/8/11
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State Minimization
In general, except for extremely simple machines, the first state diagram we write down will not be minimal viz vending machine example.
Reset S0 N S1 N S3 N
S7 [Open]
Reset 0 D S2
ECE52 Spring 11 Lecture 29
3/28/11 Midterm 2 4/8/11
1
State Minimization
In general, except for extremely simple machines, the first state diagram we write down will not be minimal viz vending machine example.
Reset S0 N S1 N S3 N
S7 [Open]
Reset 0 D S2
ECE52 Spring 11 Lecture 28
3/25/11 Midterm 2 4/8/11
1
Again, we can just specify behavior! 4-bit up-counter w/enable and reset: nb count is internal (signal)
since OUT values can't be used in an expression
Counters could specify structurally in terms of