ECE 261: CMOS VLSI Design Methodologies
Fall 2011
Krish Chakrabarty
Homework 1
Assigned: September 06, 2011
Due: September 15, 2011 (start of class)
Instructions:
You are required to work on the homework on your own. If you think a question has several
in
CMOS Testing-2
Design and test
Design for testability (DFT)
Scan design
Built-in self-test
IDDQ testing
Krish Chakrabarty
ECE 261
1
Design and Test Flow: Old View
Test was merely an afterthought
Specication
Design
errors
Design
Random
defects
Synthe
Sequential Circuit Design:
Part 1
Design of memory elements
Static latches
Pseudo-static latches
Dynamic latches
Timing parameters
Two-phase clocking
Clocked inverters
Krish Chakrabarty
1
Sequential Logic
FFs
LOGIC
Ou t
tp,comb
In
2 s to rag e me c
10/24/11
Sequential Circuit Design:
Part 2
C2MOS Latch
Two-phase clock generators
Four-phase clocking
Pipelining and NORA-CMOS
TSPC logic
1
C2MOS Logic
Goal: Make circuit operation independent of phase
overlap
No need to worry about careful design of cl
Scaling
Transistors
Interconnect
Future Challenges
Krish Chakrabarty
1
Scaling
The only constant in VLSI is constant change
Feature size shrinks by 30% every 2-3 years
Transistors become cheaper
Transistors become faster
Wires do not improve
(and
DC Transfer Characteristics,
Noise Margins, and Transient
Response
1
Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
2
1
Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor
MOS Transistor Theory
So far, we have viewed a MOS transistor as an
ideal switch (digital operation)
Reality: less than ideal
1
Introduction
So far, we have treated transistors as ideal
switches
An ON transistor passes a nite amount of current
Depend
Nonideal
Transistor
Theory
Outline
Nonideal Transistor Behavior
High Field Effects
Mobility Degradation
Velocity Saturation
Channel Length Modulation
Threshold Voltage Effects
Body Effect
Drain-Induced Barrier Lowering
Short Channel Effect
Leakag
Domino Logic
6.371 Fall 2002
10/9/02
L11 Domino Logic 1
Tinkering with Logic Gates
Things to like about CMOS gates: easy to translate logic to fets rail-to-rail switching good noise margins, no static power since fets are in cutoff sizing not critical to