ECE 25
Lab 1
Introduction to equipment, simple logic
Introduction
The goal of this lab is to introduce the equipment you will use in both ECE 25 and
ECE 35. This equipment includes power supplies, function generators, oscilloscopes, and
digital multimeter
Oscar Tellez-Salgado A10611014
Michael Wu
A98054782
Monday 7pm-10pm
WLH 2211
Introduction
The purpose of this lab is to introduce the equipment that will be used in both ECE 25 as well as ECE 35.
These equipment include power supplies, oscilloscopes, func
November 26, 2014 7:00 - 10:00 PM
ECE 25, Section: 819072
A54
ECE 25 Lab 4:
Purpose:
The purpose of this lab was to design a circuit with Xilinx that will detect a start, zero, and
one bit from a Sony IR remote. A IR receiver picked up the signal from the
ECE 25
Lab 3
Seven Segment Display
Introduction
Goal: Design a circuit using Project Navigator that will control a seven segment display on the
board. The pinout for each segment (a-g) is given on the Basys Reference Manual (pg. 4) on the
Lab Web site. We
December 10, 2014 7:00 - 10:00 PM
ECE 25, Section: 819072
A54
ECE 25 Lab 5: Storing the IR Code in a Shift Register
Purpose:
The purpose of this lab is to represent information from a remote onto a Basys Board LEDs using
coded shift registers.
Procedure:
ECE 25 - Winter 2015
Homework #3
1. A logic network has four inputs (I 3 , I 2 , I 1 , I 0 ) and two outputs (O 0 , O 1 ). At least one of the inputs
is always asserted high (logic 1). If a given input has a logic 1 applied to it, then the output signal
w
ECE 25
Lab 4
Sequential Circuits, Sequence Recognizer
Introduction
Goal: Design a circuit to recognize the start bit and data bits for a Sony IR remote. This logic
will then be used in Lab 5 to design a circuit to load the code from the remote into a shif
Homework Set 6, ECE 25, Fall 2013
The following are taken from chapter 5 problems in Mano and Kime, 4th Edition.
1. The circuit given in the following gure is to be redesigned to cut its cost.
(a) Find the state table for the original circuit and replace
ECE 25 Lab 4 Sequential Circuits, Sequence Recognizer
Introduction
Goal: Design a circuit to recognize the start bit and data bits from a Sony IR remote.
We will design a circuit, with Xilinx, to detect the start bit and data bits as they are
transmitted.
ECE 25 Lab 3
Seven Segment Display Introduction
Goal: Design a circuit using Xilinx that will control a seven-segment display on
the board. The pin out for each segment (a-g) is given on the Basys Reference
Manual (pg. 4) on the Lab Web site. We will use
1) Two-level logic minimization (10 pts)
Suppose
G(A, B, C, D) =
and suppose
m(1, 3, 4, 6, 9, 11, 14, 15)
F (A, B, C, D) = G
CD
00 01 11 10
AB
00
1
0
0
1
01
0
1
1
0
11
1
1
0
0
10
1
0
0
1
a) Identify all the prime and essential prime implicants for the fun
ECE 25 Lab 2
3-Bit Exclusive-Or Gate
Introduction:
The goal of this lab is to generate our first design using the programmable chip by
implementing a 3-bit XOR gate. We also generate the same gate by using the NAND
gates introduced in Lab 1.
Prelab:
Goal:
1) Number representation (10 pts)
a) Convert the following binary numbers to unsigned decimal numbers (e.g., 1000 = 8):
100
0000000000000001
111111
101010
4
1
63
42
b) Convert the following numbers to a 5-bit 2s complement binary representation (e.g. 3 =
Sample Midterm Questions for rst midterm
1. Assume you are given the hexadecimal number (3A5)16 . What is this number expressed in binary?
(a) (101000110111)2
(b) (101010101010)2
(c) (1110100101)2
(d) none of the above
Answer : (3)16 = (0011)2 , (A)16 = (
1) Two-level logic minimization (10 pts)
Consider the logic diagram shown below.
A
B
C
T=A'B+AC
0
1
B
W=B'T+BD
0
D
1
C
D
1
F=B'(A'B+AC)+BD+C'D+CB
F
=AB'C+BD+C'D+CB
0
B
OR
X=C'D+CB
a) Please ll out the following K-map for F as a function of A, B, C, and D.
Sample midterm problems for second midterm
1. Assume that you are given the following truth table for an encoder circuit:
D0
1
0
0
0
0
D1
X
1
0
0
0
D2
X
X
1
0
0
D3
X
X
X
1
0
A1
0
0
1
1
X
A0
0
1
0
1
X
V
1
1
1
1
0
What are the Boolean Equations for the outp
Sample midterm problems for rst midterm
1. (multiple choice) Assume you are given the hexidecimal number (A7C8)16 . What is this number expressed in
Octal?
(a) (123456)8
(b) (123614)8
(c) (123710)8
(d) (1010011111001000)2
Answer: First convert to binary,
Final Exam Guide
ECE 25, Spring 2008
Thursday, June 12, 2008
Name:
PID:
Problem
1
2
3
4
5
6
7
8
9
Total
Points
10
10
10
10
10
10
10
10
10
90
Score
1) Number representation (10 pts)
a) For each binary vector below, what does it represent as an Octal number
1) Delay Analysis (10 pts)
Assume 2 ns gate delay for 2-AND. Assume the positive edge-trigged ip-op delay is
TdelayF F = 1 ns and setup time is also TsetupF F = 1 ns.
A
B
C
D
E F
3
3
5
S3+ 7
S2+ 5
S1+ 3
S0+ 2
D-FF
D-FF
D-FF
D-FF
1
1
1
1
S3
S2
S1
What are
Final Exam
ECE 25, Spring 2008
Thursday, June 12, 2008
Name:
PID:
Problem
1
2
3
4
5
6
7
8
9
Total
Points
10
10
10
10
10
10
10
10
10
90
Score
1) Number representation (10 pts)
a) For each binary vector below, what does it represent as an Octal number and a
Homework Set 2
ECE 25 Spring 2016
Department of Computer and Electrical Engineering
University of California, San Diego
Zhaowei Liu
1.
2.
1
3.
4.
5.
6.
2
Homework Set 3 Answers
ECE 25 Spring 2016
Department of Computer and Electrical Engineering
University of California, San Diego
Zhaowei Liu
1.
2.
3.
4.
1
5.
6.
2
Homework Set 1 Answers
ECE 25
Department of Computer and Electrical Engineering
University of California, San Diego
Zhaowei Liu
1.
Binary
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Decimal
16
17
18
19
2
Homework Set 2
ECE 25 Spring 2016
Department of Computer and Electrical Engineering
University of California, San Diego
Zhaowei Liu
1. Prove the following identities using algebraic manipulation:
(a) XY + XY + XY = X + Y
(b) AB + BC + AB + BC = 1
(c) Y +