ECE 235, HW-2
Spring 2016
1.
Consider a uniformly doped nMOSFET of Na = 1018 cm-3 biased at the threshold
condition. Calculate the first three quantum mechanical energy levels for inversion electrons in
the lower valley with effective mass of 0.92m0 where
ITRS Roadmap of CMOS Generations
Minimuum Featurre (m)
General litho
?
year
4/28/2014
1
Limit of Bulk CMOS Scaling
Quantum mechanical tunneling
Gate insulator
Band to band (Zener)
Source to drain
Thermal
Th
l voltage
lt
off electrons
l t
kT/q ~ 0.02
ECE 235, HW-3
Spring 2016
1. Consider a symmetric double-gate nMOSFET with tox=2(nm), tsi=10(nm). The gate workfunctions
are qm = 4.33(eV ) (half way between n+ Si and intrinsic Si).
(a) Plot Ids vs. Vds for the range of 0<Vds<2(V), with Vgs=0, 0.5, 1, 1.
ECE 235, HW-4
Spring 2016
1. Explain the Inverter-1 transfer curve of SRAM cell during a WRITE operation.
Solution:
When the input voltage to the inverter on the left is zero, Q1 is off and Q3 is on.
However, Q5 is also on during WRITE. So the voltage fro
ECE 235, HW-1
Spring 2016
1.
In the parabolic potential model, the solution to
2 2
q
+ 2 =
Na
2
x
y
si
is assumed to be of the form ( x, y ) = a ( y ) + a ( y ) x + a ( y ) x 2
0
1
2
Apply the top and bottom boundary conditions (continuity of vertical d
ECE 235, HW-2
Spring 2016
1.
Consider a uniformly doped nMOSFET of Na = 1018 cm-3 biased at the threshold
condition. Calculate the first three quantum mechanical energy levels for inversion electrons in
the lower valley with effective mass of 0.92m0 where
ECE 235, HW-1
Spring 2016
1.
In the parabolic potential model, the solution to
2 2
q
+ 2 =
Na
2
si
x
y
is assumed to be of the form ( x, y ) = a ( y ) + a ( y ) x + a ( y ) x 2
0
1
2
Apply the top and bottom boundary conditions (continuity of vertical d
ECE 235, HW-3
Spring 2016
1. Consider a symmetric double-gate nMOSFET with tox=2(nm), tsi=10(nm). The gate workfunctions
are qm = 4.33(eV ) (half way between n+ Si and intrinsic Si).
(a) Plot Ids vs. Vds for the range of 0<Vds<2(V), with Vgs=0, 0.5, 1, 1.
ECE 235, HW-4
Spring 2016
1. Explain the Inverter-1 transfer curve of SRAM cell during a WRITE operation.
2. Consider an nMOS floating gate NVRAM device with 12 nm thick interpoly oxide between the
control gate and the floating gate and 10 nm thick tunnel
ECE 235: Spring 2016
N
Nanometer-Scale
t S l VLSI Devices
D i
Professor Yuan Taur
Electrical & Computer Engineering
University of California, San Diego
3/27/2016
Yuan Taur
1
ECE 235: Spring 2016
Nanometer-Scale VLSI Devices
Prerequist: ECE 103, 135B, or 2