ECE 164
Homework #3
Due Tuesday Nov. 12, 2013 InClass. No late homeworks accepted.
PROBLEM 1
Current Mirror Mismatch. We found that the standard current mirror had several
sources of mismatch due to voltage and process variations. 20 PTS
a. Find the wors
ECE 164
Homework #4
Due Tuesday Nov. 19, 2013 InClass. No late homeworks accepted.
PROBLEM 1
Common Source Amplifier with Current Source Load. Consider an NMOST
common source device with W/L of 10 and PMOST load with W/L of 10. You may
always use paramet
ECE 164 Fall 1516
D. Hall
Page 1 of 2
Homework #4
Due: Thursday, November 5th, 11:00 AM
1. Magic Battery Biasing [15 pts]
Consider the circuit shown below. This is the circuit that was shown in several of the biasing schemes shown
in lecture. Remember th
ECE 164 Fall 1516
D. Hall
Page 1 of 3
Homework #5
Due: Thursday, November 12th, 11:00 AM
1. Cacoded Amplifier with Replica Bias [20 pts]
Consider the circuit shown below. For all parts of the problem, use (W/L)0,1,2 = 4, (W/L)3 = 1/n(W/L)1, (i.e.,
the L
ECE 164 Fall 1516
D. Hall
Page 1 of 7
Homework #2
Solutions
1. Transit frequency
From the above small signal model with the output node (drain) shorted to ground, derive the KCL
equation at the gate and drain node:
, =
=
= ( )
= +
= +
= ( + )
With t
ECE 164 Fall 1516
D. Hall
Page 1 of 3
Homework #5
Solutions
4. Amplifier Design
From previous homework, the parameter are:
430 for L = 1
,
285
,
62
,
,
400
, and
Topology
Use a CommonSource amplifier with active loading for 40dB gain. Also, use pMOS in
ECE 164 Fall 1516
D. Hall
Page 1 of 3
Homework #4
Solutions
5. Amplifier Design
Topology
Use a CommonDrain amplifier for this design to drive low resistor load.
Current mirror
Input stage
ID
Icurrent_mirror
AC SPEC


0.7
 /

4.2
.
(Overdesign the g
ECE 164 Fall 1516
D. Hall
Page 1 of 2
Homework #2
Due: Thursday, October 15th, 11:00 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resistance, backgate effect, etc. unless otherwise stated.
1.
Q4(b)
Q4(c)
Q5. Cadence Tutorial
Schematic:
DC Operating Point:
DC Sweep of Vin (Vin = 470mV):
DC Operating Point (Vout = Vdd/2 = 1.25V)
Transient Analysis
AC Analysis
Q6 Technology Characterization
(a) nMOS Test Schematic
nMOS ID vs. VGS (in both linear
Q4. The DC operating point with a differential input of 100uV.
Sizing of each transistor is shown below:
AC plot for the overall transfer function and transfer function of each stage:
Transient plot of the differential input and singleended output:
ECE 164
Homework #2
Due Tuesday Oct. 22, 2013 InClass. No late homeworks accepted.
PROBLEM 1
CMOS Sample and Hold. Solve based on the 0.25um CMOS process that we are
using for the class. Assume that the supply voltage is 2.5 V. 30 PTS
a. Choose the trans
ECE 164
Homework #1
Due Thursday Oct. 10, 2013 InClass. No late homeworks accepted.
PROBLEM 1
Below is a circuit that you may have seen from the first lecture. Let R3 be infinite.
Solve for the voltage gain. (10)
The current through R1 is
! =
and the vol
ECE 164 Fall 1617
D. Hall
Page 1 of 2
Homework #2
Due: Thursday, October 13th, 9:30 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resistance, backgate effect, etc. unless otherwise stated.
1.
ECE 164 Fall 1617
D. Hall
Page 1 of 2
Homework #1
Due: Thursday, October 6th, 9:30 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resistance, backgate effect, etc. unless otherwise stated.
1. P
ECE 164 Fall 1516
D. Hall
Page 1 of 2
Homework #1
Due: Thursday, October 8th, 11:00 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resistance, backgate effect, etc. unless otherwise stated.
1.
Note: Correction to Q3) d) final answer: The requirements in part c) do not hold, as the Vov of the
transistors is different from the previous part. This changes the input voltage ranges.
Q5) Designing the Filter with frequency: 120 MHz
Determining Cox:
W
ECE 164 Fall 1516
D. Hall
Page 1 of 9
Homework #1
Solutions
1. Plain Old NMOS
1
2
a) = 2 ( )
2
2 300A
( )= 2 =
= 48
50A (500)2
b) =
> (keep nMOS in saturation region)
50.5
< =
= 15
300A
The nMOS enters triode region and the current reduces signif
Note: Correction: For Case 2) in Q1)a) M2 is in triode, Q1)c) There is an additional Vtn term to be
added to the final expression for VB.
Therefore Icurr_mirr = Id  IRL = 250.7 uA.
Plots:
DC Operating point:
AC analysis: Gain = 3.79 dB, 3dB BW = 3.01Mh
ECE 164
Homework #5
Due Friday Dec. 6, 2013 by 5 PM. Turn homework into the shelf outside Prof.
Buckwalters office (EBUI 5706). No late homeworks accepted.
PROBLEM 1
In this problem, you will design a twostage operational amplifier based on your
knowled