ECE 164 Fall 15-16
D. Hall
Page 1 of 7
Homework #2
Solutions
1. Transit frequency
From the above small signal model with the output node (drain) shorted to ground, derive the KCL
equation at the gate
ECE 164 Fall 15-16
D. Hall
Page 1 of 2
Homework #1
Due: Thursday, October 8th, 11:00 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resistan
ECE 164
Homework #3
Due Tuesday Nov. 12, 2013 In-Class. No late homeworks accepted.
PROBLEM 1
Current Mirror Mismatch. We found that the standard current mirror had several
sources of mismatch due to
ECE 164
Homework #4
Due Tuesday Nov. 19, 2013 In-Class. No late homeworks accepted.
PROBLEM 1
Common Source Amplifier with Current Source Load. Consider an NMOST
common source device with W/L of 10 an
ECE 164 Fall 15-16
D. Hall
Page 1 of 3
Homework #5
Due: Tuesday, November 17th, 11:00 AM
1. Cacoded Amplifier with Replica Bias [20 pts]
Consider the circuit shown below. For all parts of the problem,
ECE 164 Final Design Project
Transimpedance Amplifier
12/1/2015
Da Ying
A97039073
[email protected]
Xiuyuan Lu
A53088443
[email protected]
ECE 164 Analog Design Final Project Report
Abstract:
In th
ECE 164 Fall 15-16
D. Hall
Page 1 of 2
Design Project
Due: Tuesday, December 1st, 11:00 AM
Your first project at Triton Industries, Inc. is to redesign a sensor interface using a new technology. The
s
ECE 164
Homework #5
Due Friday Dec. 6, 2013 by 5 PM. Turn homework into the shelf outside Prof.
Buckwalters office (EBUI -5706). No late homeworks accepted.
PROBLEM 1
In this problem, you will design
Lecture 4:
Small-Signal Model
Prof. Drew Hall
[email protected]
ECE 164 Analog Integrated Circuit Design
Lecture slides incorporate material from Profs. Murmann (Stanford), Dutton (Stanfrod), Mitra
(S
Lecture 1:
IC Technology
Prof. Drew Hall
[email protected]
ECE 164 Analog Integrated Circuit Design
Lecture slides incorporate material from Profs. Murmann (Stanford), Dutton (Stanfrod), Mitra
(Stanfo
Lecture 2:
Long Channel MOS Physics
Prof. Drew Hall
[email protected]
ECE 164 Analog Integrated Circuit Design
Lecture slides incorporate material from Profs. Murmann (Stanford), Dutton (Stanfrod), Mi
Lecture 3:
Common Source Amplifiers
Prof. Drew Hall
[email protected]
ECE 164 Analog Integrated Circuit Design
Lecture slides incorporate material from Profs. Murmann (Stanford), Dutton (Stanfrod), Mi
Lecture 5:
Frequency Response
Prof. Drew Hall
[email protected]
ECE 164 Analog Integrated Circuit Design
Lecture slides incorporate material from Profs. Murmann (Stanford), Dutton (Stanfrod), Mitra
(S
ECE 164 Fall 15-16
D. Hall
Page 1 of 3
Homework #4
Solutions
5. Amplifier Design
Topology
Use a Common-Drain amplifier for this design to drive low resistor load.
Current mirror
Input stage
ID
Icurren
ECE 164
Homework #2
Due Tuesday Oct. 22, 2013 In-Class. No late homeworks accepted.
PROBLEM 1
CMOS Sample and Hold. Solve based on the 0.25um CMOS process that we are
using for the class. Assume that
ECE 164
Homework #1
Due Thursday Oct. 10, 2013 In-Class. No late homeworks accepted.
PROBLEM 1
Below is a circuit that you may have seen from the first lecture. Let R3 be infinite.
Solve for the volta
ECE 164 Fall 16-17
D. Hall
Page 1 of 2
Homework #2
Due: Thursday, October 13th, 9:30 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resistan
ECE 164 Fall 16-17
D. Hall
Page 1 of 2
Homework #1
Due: Thursday, October 6th, 9:30 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resistanc
Note: Correction to Q3) d) final answer: The requirements in part c) do not hold, as the Vov of the
transistors is different from the previous part. This changes the input voltage ranges.
Q5) Designin
Note: Correction: For Case 2) in Q1)a) M2 is in triode, Q1)c) There is an additional Vtn term to be
added to the final expression for VB.
Therefore Icurr_mirr = Id - IRL = 250.7 uA.
Plots:
DC Operatin
Q4. The DC operating point with a differential input of 100uV.
Sizing of each transistor is shown below:
AC plot for the overall transfer function and transfer function of each stage:
Transient plot o
ECE 164 Fall 15-16
D. Hall
Page 1 of 2
Homework #2
Due: Thursday, October 15th, 11:00 AM
For all problems, use simple long channel MOS models. Ignore second order effects such as finite output
resista
ECE 164 Fall 15-16
D. Hall
Page 1 of 2
Homework #4
Due: Thursday, November 5th, 11:00 AM
1. Magic Battery Biasing [15 pts]
Consider the circuit shown below. This is the circuit that was shown in sever
ECE 164 Fall 15-16
D. Hall
Page 1 of 3
Homework #3
Due: Tuesday, October 27th, 11:00 AM
1. NMOS Bias Circuit Amplifier [15 pts]
Consider the circuit shown below. For all calculations, assume kn = 250
ECE 164 Fall 15-16
D. Hall
Page 1 of 3
Homework #5
Due: Thursday, November 12th, 11:00 AM
1. Cacoded Amplifier with Replica Bias [20 pts]
Consider the circuit shown below. For all parts of the problem
ECE 164 Fall 15-16
D. Hall
Page 1 of 3
Homework #5
Solutions
4. Amplifier Design
From previous homework, the parameter are:
430 for L = 1
,
285
,
62
,
,
400
, and
Topology
Use a Common-Source amplifi