ECE 366 Computer Organization II
Spring 2017 - UIC
Homework 3 - Solutions
Pr.1)
Pr.2) The answer is the same for both cases, as in the 2s complement format, it is a
positive number.
0x0C000000 = 12 x 16 ^ 6 = 201326592
Pr.3) 0000 1100 0000 0000 0000 0000
ECE366
Computer Design and Organization
Spring 2014
Lab - 3
February 11, 2014
1
Goal
The goal of this lab is to continue to make yourself familiar with simple combinational logic design in Verilog,
and to learn how to translate from Gate-Level Design to V
ECE366
Computer Design and Organization
Spring 2014
Lab - 7
March 11, 2014
1
Goal
The goal of this lab is to add memory operations to your processor.
2
Arithmetic Logic Unit
The memory operations are fundamental in any instruction set architecture (ISA).
ECE366
Computer Design and Organization
Spring 2014
Lab - 1
January 28,2014
1
Goal
The goal of this lab is to familiarize you with basic logic design in Verilog, as well as the Modelsim simulation
tool.
2
2.1
Requirements
Review material
Review the follow
ECE366
Computer Design and Organization
Spring 2014
Lab - 4
Frbruary 18, 2014
1
Goal
The goal of this lab is to build sequential circuit module - Register File.
2
D Flipflop
The following is an example of verilog implementation of D-Flipflop. Write testbe
ECE366
Computer Design and Organization
Spring 2014
Lab - 10
April 8, 2014
1
Goal
The goal of this lab is to study how to program hardware in behavior description.
2
Behavioral programming
We have written past Verilog modules from the structural point of
ECE366
Computer Design and Organization
Spring 2014
Lab - 2
Frbruary 4, 2014
1
Goal
The goal of this lab is to continue to make yourself familiar with simple combinational logic design in Verilog,
and build a first component in an ALU.
2
Adder
An adder is
ECE366
Computer Design and Organization
Spring 2014
Lab - 5
February 25, 2014
1
Goal
The goal of this lab is to build an Arithmetic Logic Unit.
2
Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) is a fundamental building block of any CPU. It is desig
ECE366
Computer Design and Organization
Spring 2014
Lab - 6
March 4, 2014
1
Goal
The goal of this lab is to build the data path for arithmetic operations.
2
Arithmetic Logic Unit
The arithmetic operations supported in an Instruction Set Architecture (ISA)
ECE366
Computer Design and Organization
Spring 2014
Lab - 8
March 18, 2014
1
Goal
The goal of this lab is to add a fetch unit to your processor.
2
Instruction Memory
The instruction memory is the first component in any datapath. It enables the processor t
Homework 3 Solutions
C.1.b Without forwarding:
1
2
3
LD R1, 0(R2)
F
D X
DADDI R1, R1, #1
F
D/S
4
5
M
W
D/S D
6
X
7 8 9
M W
SD R1, 0(R2)
DADDI R2, R2, #4
F/S
S
Homework 5
1. Assume the computer has a pool of temporary registers (T0 through T31).
Consider the code sequence below. Use register renaming to remove all the WAR
and WAW hazards, beginning with temporary regist
University of Illinois at Chicago
ECE 366 Computer Organization II
SPRING 2017
Instructor: Paolo Vinella
TAs: Vahid Foroutan
Homework 1 Solution
PROBLEM #1 [15/100 Points]
Compilers perform the translation of a program written in a high-level language, su
University of Illinois at Chicago
ECE 366 Computer Organization II
SPRING 2017
Instructor: Paolo Vinella
TAs: Vahid Foroutan
Homework 2 Solution
PROBLEM #1 [5/100 Points]
PROBLEM #2 [10/100 Points]
PROBLEM #3 [10/100 Points]
a.
b.
c.
d.
Homework 2 Solutio
Homework 6
3.15.b
(1) With speculation; and assume the outcome of branch instruction is correctly
predicted.
(2) Assume there is an integer ALU for address calculation; and another integer ALU
for branch and all
A.1
Homework 2 Solution
For gap and gcc, the average instruction frequencies are below:
Instruction
Average of gap and gcc (%)
load
25.8
store
11.8
add
20.0
sub
2.0
mul
0.8
compare
4.4
load imm
3.6
cond branch
10.7
cond move
0.5
jump
0.8
cal
Homework 4
In this exercise, we look at how software techniques can extract instruction-level
parallelism (ILP) in a common vector loop. The following loop is the so-called DAXPY
loop (double-precision aX plus Y) and is the central operation in Gaussian
Quiz 6
Assume the following 10-bit address sequence generated by the microprocessor:
The cache uses 4 bytes per block. Assume a 2-way set associative cache design
that uses the LRU algorithm (with a cache that can hold a total of 4 blocks). Assume
that th
ECE366
Computer Design and Organization
Spring 2014
Lab - 9
April 1, 2014
1
Goal
The goal of this lab is to make your processor support a new conditional branch operation.
2
Branch Operations
The branch type of instructions is a main part of any instructi