ENEE 303 (Horiuchi)  Exam #1 SOLUTIONS
E1) The pnjunction diode
a) (1 pt) In the pnjunction diode, there are two capacitances that affect highfrequency operation. What are the
names of these two capacitances and what is their physical origin?
The diff
Homework #1 ENEE 303
(Horiuchi, Fall 2011)
Due: Tuesday, Sept 6th, 2011 (in class)
Your goal in the homework is to both explain to me how one solves the problem and to solve for the
actual answer. Correct final answers are only a part of the solution. Be
HW1 solns sheet Horiuchi
(1) Note that the wire in the center can have current running through it, but it will be all at the
same potential. Lets call the potential on this node, Vx. In this problem, the circuit can be
collapsed into two series resistors
HW #1 solutions sheet Horiuchi
(1) Note that the wire in the center can have current running through it, but it will be all at the same potential.
Lets call the potential on this node, Vx. In this problem, the circuit can be collapsed into two series resi
ENEE 303 (Horiuchi) Exam #1 SOLUTIONS
In this exam, we will be ignoring the Early effect and the body effect.
E1) CV diode model
Use the CV model of the diode with a threshold voltage of V0.
Assume that Vdd is > 2 V0. Assume there is current r
ENEE 303 Midterm Exam 1
Solution
1. Shows that for the inverting amplifier if the opamp gain is A, the input resistance is given by
= 1 +
2
+1
R2
ii
vi
R1
v
vo
v+
Fig. 1
Solution:
= = 2 (5 )
2 = (1 + ) (5 )
=
2
(5 )
1+
Again
= 1 + = 1 +
2
(5 )
1
ENEE 303: Analog and Digital Electronics
Spring 2015, Homework 2
Due Date: March 10, 2015
Problem 1. For the circuits shown in Fig. 1 using ideal diodes, find the values of the
labeled voltages and currents.
Fig. 1.
Problem 2. In each of the idealdiode c
Homework #5 ENEE 303
(Horiuchi) Solution Set
1) 1 pts In the circuit on the right, a current I flows into the transistor. If we know Is, for the
transistor, give the formula describing the voltage V in terms of I. Start by indicating what mode the
transis
ENEE 303: Analog and Digital Electronics
Spring 2015, Homework 1
Due Date: Feb. 12th, 2015, 11:00am in the class.
1. A noninverting amplifier configuration, with finite opamp openloop gain A, is shown
in Fig.1. Derive the closedloop gain (G =Vo/Vi) of
Homework #1 ENEE 303
(Horiuchi, Fall 2014)
Due: Tuesday, Sept 9th, 2014 (in class)
Your goals in the homework are to: 1) explain to me how one solves the problem, and 2) to solve for
the actual answer. Correct final answers are only a part of the
Homework #2 Solutions
ENEE 303
Problem 1  If a diode passes 0.6 mA at 0.681v, then we can solve for Is.
0.600mA = I s e
0.681
25.8 mV
Is = 2.06E15 A
We know that the current will be less then 1mA because 6V / 6K is already 1mA and we didnt take into acc
ENEE 303 (Horiuchi) Exam #1 Solution Set
E1) CV diode model
Use the CV model of the diode with a threshold voltage of VD0.
1a) (1 pt) Solve for the inequality that indicates when D1 is conducting current. (i.e., D1 conducts
current when xxxxxx >
Homework #8 ENEE 303 (F2010)
Problem 1 Input resistance
Commondrain amplifier
va
ia
Rin =
Rin =
ia =
1
va va
1
+
= va +
R1 R2
R1 R2
va
1
=
= R1  R2
1
1
ia
+
R1 R2
Commonsource amplifier
Rin =
va
ia
ia =
va vb
v
v
v
= g m1 (va 0) + b + b + b
R1
r01
ENEE 303 Homework #10 Solution Set
1) 1 pts In the circuit on the right, a current I flows into the transistor. If we know Is, for the
transistor, give the formula describing the voltage V in terms of I. Assume that the transistor
is in the forward a
ENEE 303 (Horiuchi)  Exam #2
Some helpful equations
iC = I S e
vBE
VT
g m = kn '
,
=
+1
iB + iC = iE
,
ln(ab) = ln(a) + ln(b) , I D = kn '
W
1 2
( vGS Vt ) vDS 2 vDS
L
W
(VGS Vt ) , r = / g m , re = / g m , a ln x = ln x a
L
E1) BJT amplifier DC and sm
Homework #8 (Horiuchi) Fall 2013 Solution Sheet
Vdd
Due: Tuesday, November 19, 2013 (in class)
M2
3*IB
V2
Problem #1 folded cascode
(3 pts) In the circuit on the right, V1, V2, and V3 are all fixed DC
M3
voltages. M2 provides the DC current (3*IB)
Homework #7 MOSFETS
ENEE303 (Horiuchi)
9v
Problem 1  MOSFET
(1pt) In the MOSFET circuit on the right, if we want to pull V2 down to the
edge of saturation, what gate voltage will we have to apply? kn = 50uA/V2
and Vt = 0.8 and W/L = 10. Ignore the Early
ENEE 303 Homework 4
Problem 1. Consider a CMOS process for which Lmin 0.25 m, tox 6nm,Vt 0.5V and
n 460cm2 / V s .
(a) Find Cox and k n .
(b) For an NMOS transistor with W / L 15 m / 0.25 m , calculate the values of VOV ,VGS
and VDSmin needed to operate t
ENEE 303 Homework 2
Problem 1. Use the iterativeanalysis procedure to determine the diode current and voltage in the
circuit of Fig. 1 for VDD = 1 V, R = 1k, and a diode having Is = 1015A.
ID
R
VD
VDD
Fig. 1
Problem 2. In the circuit shown in Fig. 2, I
ENEE 303 Midterm Exam 2 Solution
1. Explain NMOS operation modes and provide iD equations in each operating mode. (20 points)
Solution:
a) Cut off region
When VGS < Vth.
The transistor is turned off. iD = 0.
b) Triode region
(2 points)
(2 points)
When VGS
ENEE 303 Homework 1 Solution
Problem 1.
(a) In order to find out the input resistance Rix, we need to place a test signal vt in the input
terminal and try to find out the test current it. The input resistance is Rix = vt/it.
R2
vt
i1
it R
1 vx
i2 R
Rix
Ro
I
_/_1
13.3
MH
1
V
VOh
=
VDD
8
O.
,
1
V
NML
(04
VOL
width of transition region
V,.H
=
DD
61
0.1 )VDD
_
,
0
O.3V
00
O.2V for a minimum NM of
VIL
lv =O
VDD
2
I
5 V
VDD
!i:
13.23
Note that this question ignores the possibility ol
dynamic power dissipation Av
_
P
I
i
A
5.10 L
0.25 jim
=
5.50
6
=
2
Ii n
(a)
460
0
C
2
ro )
,3
+2.5V.
vs
345 pF/rn
=
=
460 x
=

0.25mA
R
6nm
5.75 x io
=
+1 .8V.
m
k
0
C
= ji
(b)For
=
265 (A)/v
2
=
20,k
=
5.29 mA/V
2
+1 .OV.
.0.8mA=iD=!kflv(.
=
VGS
055 V
=
1.05 V.
VDSO.SSV
g
(c)
=
k
4.46
The dc current I flows through the diode giving
4.33
R
=
I k2
rise to the diode resistance
r
j= !i1
I)
and the
SmallSignal equivalent circuit is represented by
R
+
0
rdV
I0_2 mA
A
5
I0
Use Iterative Analysis
procedure
I V
V,ID
7
O.
=
2 VD
Vo
0.3 mA
ENEE 303 Homework 3
Problem 1. Consider an npn transistor operated in the active mode and represented by the model
of Fig 1(a). Let the transistor be connected as indicated by the equivalent circuit shown in Fig 1(b).
It is required to calculate the value
File G/courses/F2012/303/303F12hmrk4.doc
RWN 09/23/12
303 Fall 2012
Homework 4 due 10/02/12
1. 50 points (PMOS biasing)
Bias the PMOS 4007 in the following circuit to have a Q point at VGS=3V,
VDS=5V. For this assume an RS=50, Vdd=9V, and one of Ra or R