EECS 361
Midterm Solutions
-1 point for any incorrect calculation.
Q1) System Performance (20 points)
The base system spends 82% of the time computing and 18% of the time waiting for the
disk. Integer instructions (40% of executed instructions) have a CPI
Homework #3 Solutions (abridged)
1)
Loads
Stores
R-type
Branch
RegDst=0
Y
Y
N
Y
ALUSrc=0
N
N
Y
Y
MemtoReg=0
N
Y
Y
Y
Zero=0
Y
Y
Y
N
RegDst=1
N
Y
Y
Y
ALUSrc=1
Y
Y
N
N
MemtoReg=1
Y
Y
N
Y
Zero=1
Y
Y
Y
N
2)
Loads
Stores
R-type
Branch
3)
The gcc data from Chapt
361
Computer Architecture
Lecture 8: Designing Single Cycle Control
361 control.1
Outline of Todays Lecture
Recap and Introduction
Complete the datapath: Branch/Jump instructions
Control for Register-Register & Or Immediate instructions
Control signal
EECS 361
Computer Architecture
Lecture 5
The Design Process, ALU Design
361 design.1
Quick Review of Last Lecture
361 design.2
MIPS ISA Design Objectives and Implications
Support general OS and Cstyle language needs
Support general and
embedded applicatio
EECS 361
Computer Architecture
Lecture 10: Designing a Multiple Cycle Controller
361 multicontroller.1
Review of a Multiple Cycle Implementation
The root of the single cycle processors problems:
The cycle time has to be long enough for the slowest instr
EECS 361
Computer Architecture
Lecture 1
Prof. Gokhan Memik
[email protected]
Course slides developed in part by Profs. Hardavellas, Hoe, Falsafi, Martin, Roth,
Lipasti, Goldstein, Mowry
EECS 361
1-1
What is Computer Architecture?
Computer archi
EECS 361
Computer Architecture
Lecture 2 - Performance
Prof. Gokhan Memik
[email protected]
Course slides developed in part by Profs. Hardavellas, Hoe, Falsafi, Martin, Roth,
Lipasti, Goldstein, Mowry
2-1
Four Lessons from the Previous Class
Imp
EECS 361
Computer Architecture
Lecture 4 MIPS ISA
361 Lec4.1
Todays Lecture
Quick Review of Last Lecture
Basic ISA Decisions and Design
Operations
Instruction Sequencing
Delayed Branch
Procedure Calling
361 Lec4.2
Quick Review of Last Lecture and Ca
Lecture 13
Pipeline Implementation Pragmatics:
Branch Prediction,
Exception Handling
Adapted from slides developed by Profs. Hardavellas, Falsafi, Hill, Marculescu, Patterson, Rutenbar and
Vijaykumar of Northwestern, Carnegie Mellon, Purdue, Berkeley, UWi
Computer Architecture
EECS 361
Lecture 6: ALU Design
361 ALU.1
Review: ALU Design
Bit-slice plus extra on the two ends
Overflow means number too large for the representation
Carry-look ahead and other adder tricks
A
32
B
32
signed-arith
and cin xor co
EECS 361
Computer Architecture
Lecture 11
Designing a Pipeline Processor
pipeline.1
Overview of a Multiple Cycle Implementation
The root of the single cycle processors problems:
The cycle time has to be long enough for the slowest instruction
Solution:
R F D F 2) F 5 F H 2) () H (c)c I I Hc F 5 F H 2) ) V Hc c 5 5 Hc F @ ) F 5 9 ( DD ( 2
6#E#!#4E#6Qd4E1EEEE#6Qd4E8E#6BBQQq4F
6#yx4EBdQ8v44#qQu#EBQb#f t 6Q6r!qGEQEBiQ!gQ4#be4
F D w R F) Hc ( @ h U 5 ( 7 F) H 9 ( f f I H D C ( 5 @ )c I 5 5) s H Fc p S R F)
Homework 4 Solutions
Problem 1
Reference Hit or miss
Reference
Hit or Miss
1
Miss
4
Miss
8
Miss
5
Miss
20
Miss
17
Miss
19
Miss
56
Miss
9
Miss
11
Miss
4
Miss
43
Miss
5
Hit
6
Miss
9
Hit
17
Hit
Here is the final state of the cache:
Block # Address
Block #
Ad
ECE 361
Computer Architecture
Lecture 12
Pipeline Control
361 hazards.1
Review: A Pipelined Datapath
Clk
Ifetch
Reg/Dec
Exec
ExtOp
RegWr
Mem
ALUOp
Wr
Branch
1
0
PC
Ra
Rt
RFile
Rw Di
Rd
0
Data
Mem
RA Do
WA
Di
1
RegDst
361 hazards.2
Exec
Unit
Zero
ALUSrc
Me