SIGNALS AND SYSTEMS
Spring 2016
Assignment #2
Deadline: 06/06/2016, Final
Q1. [60 marks]
A real-value signal
characteristics:
x (t)
and its Laplace transform
a)
X (s)
has exactly two poles and one zero.
b)
X (s )
has a pole at s=2+ j .
c)
X ( s )=1
d)
x (
ECE 354 Lecture Notes, Chapter 4
4.6 Beamwidth Between First Nulls, Half Power Beamwidth, and Directivity of the
LCPESA
The Beamwidth Between First Nulls (BWFN), Half Power Beamwidth (HPBW),
and antenna directivity (D) were defined in Sections 2.7 and 2.9
ECE 354 Lecture Notes, Chapter 4
4.7 Pattern Multiplication
In Section 4.1 we found that the electromagnetic fields E(r ) radiated by an array antenna
equal those radiated by a reference element, E ref (r ) , multiplied by the array factor
ARFAC(, ) or
(4
Tutorial 5 Outline
Introduction to Arrays
The Array Factor for Linear Equally
Spaced Arrays
Linear Arrays with Specified Pattern
Nulls
Linear Uniformly Excited, Equally
Spaced Arrays
1
4.1
Introduction
Chapter
4
Arrays
This chapter will focus on array an
ECE 354 Lecture Notes, Chapter 4
4.5 Broadside and endfire arrays
A broadside array has its main beam perpendicular to the array axis. From the
graphical construction presented in Section 4.4, we conclude that for a broadside array
k o = 0 . Figure 4.13 p
ECE 354 Lecture Notes, Chapter 4
4.4 Linear Uniformly Excited, Equally Spaced Arrays.
In a Linear Uniformly Excited Equally Spaced Array (LUEESA) with constant
excitation, we choose I i = I 0 , i = 1,., N 1 , i.e., all elements are excited with the same
s
ECE 354 Lecture Notes, Chapter 4
4.2 The Array Factor for Linear Equally Spaced Arrays.
Linear Arrays consist of individual elements arranged along a straight line. In this
and the following sections, we will assume that the array consists of N elements w
Tutorial 5 Outline
Broadside and
end-fire arrays
Pattern
Multiplication
1
4.5
Broadside and end-fire arrays
A broadside array has its main beam perpendicular to the array
axis. We conclude that for a broadside array .
Figure 4.13 plots the array factor f
ECE 354 Lecture Notes, Chapter 4
Chapter 4
Arrays
4.1 Introduction
This chapter will focus on array antennas. Arrays are antennas comprised of
multiple physically identical individual elements, which are spatially arranged and excited
with respect to each
ECE 354 Lecture Notes, Chapter 4
4.3 Linear Arrays with Specified Pattern Nulls.
We may judiciously construct an array factor with nulls in specified directions
i , i = 1,., N 1 by choosing the zeros of the polynomial (4.15) as
ci = e jkd cosi , i = 1,.,
1
4.1 Introduction
This chapter will focus on array antennas. Arrays are antennas
comprised of multiple physically identical individual elements, which are
spatially arranged and excited with respect to each other in order to
create a specific directional
1
4.5 Broadside and end-fire arrays
A broadside array has its main beam perpendicular to the array axis. We
conclude that for a broadside array = 0.
Figure 4.13 plots the array factor for broadside arrays with = /2 and
varying . We observe that, for a con
Capture CIS Tutorial
CMPE 310
Ekarat Laohavaleeson
Cadence Capture CIS
Capture CIS is an EDA (Electronic Design Automation) tool. It is frequently used
to create a schematic design for PCB (Printed Circuit Board) and FPGA project. The
simple steps involve
Udo Klein
International University
Scool of Electrical Engineering
Digital Electronics EE095IU
Lab 1: BJT Logic Circuits
Full name:
_
Student ID number: _
Class:
_
Date:
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Page 1 of 11
Laboratory 1
I.
EE095IU
Objectives
The objective of this laboratory is
Udo Klein
25 Feb 2011
Digital Electronics EE094IU
Homework 2 Review of Electronic Devices
Please hand in your homework by Friday, 11 March 2011.
1.
Electrical Circuit Basics
Use voltage and current division to find V1, V2, I2, and I3 in the circuit below
Chng 3: OrCAD Capture 9.2
Chng 3: OrCAD Capture9.2
Mc tiu cn t c:
Sinh vin c th thit k mt mch in t n gin n phc tp thng qua cc mn hc
chuyn ngnh bit. Sinh vin c th m phng mch in va thit k kim chng. V c
mch in nguyn l Capture hon chnh, cch to ra mt Netlist
Udo Klein
18 Feb 2011
1.
Digital Electronics EE094IU
Homework 1 Introduction
Moores Law
The straight line in the figure below is described by N = 1,610 100.1548(Year-1970). Based on a straightline projection of this figure, what will be the number of tran
Udo Klein
25 Feb 2011
Digital Electronics EE094IU
Homework 2 Review of Electric Circuit Basics
1.
Electrical Circuit Basics
Use voltage and current division to find V1, V2, I2, and I3 in the circuit below if V = 5 V, R1 = 18 k, R2
= 22 k, and R3 = 150 k.
INTERNATIONAL UNIVERSITY (IU) VIETNAM NATIONAL UNIVERSITY HCMC
Midterm Examination
DATE: April 7th, 2011
Duration: 90 minutes
SUBJECT: Digital Electronics
Dean of School of Electrical Engineering
Signature:
Lecturer: Udo Klein
Signature:
Full name: Trn Vn
Udo Klein
25 Mar 2011
Digital Electronics EE094IU
Homework 6 NMOS Logic Design
Please hand in your homework by Friday, 1 April 2011.
1.
Dynamic Response of Logic Gates
The Intel Core i7-2600 microprocessor is fabricated in a 32-nm technology. The design r
4 Mar 2011
Udo Klein
Digital Electronics EE094IU
1.
Homework 3 Review of Solid State Diodes
pn Junction
A diode is doped with NA = 51015/cm3 on the p-type side and ND = 1019/cm3 on the n-type side.
(a) What is the depletion-layer width wd0?
(b) What are t
Udo Klein
International University
Scool of Electrical Engineering
Digital Electronics EE095IU
Lab 2: MOS Transistors
[1] Full name:
Student ID number:
[2] Full name:
Student ID number:
[3] Full name:
Student ID number:
_
_
_
_
_
_
Class:
_
Date:
_
Page 1
SN74LS74A
Dual D-Type Positive
Edge-Triggered Flip-Flop
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky
TTL circuitry to produce high speed D-type flip-flops. Each flip-flop
has individual clear and set inputs, and also complementary Q and Q
Udo Klein
International University
Scool of Electrical Engineering
Digital Electronics EE095IU
Lab 6: Flip-Flops
[1] Full name:
Student ID number:
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Student ID number:
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_
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_
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Page 1 of 8
Udo Klein
15 Apr 2011
Digital Electronics EE094IU
Homework 7 MOS Logic Design
Please hand in your homework by Friday, 29 April 2011.
1.
Pseudo NMOS Inverter
The inverter below is to be designed to have VL = 0.25 V and P = 0.2 mW. Assume Kn = 100
A/V2 for
Udo Klein
25 Mar 2011
1.
Digital Electronics EE094IU
Homework 6 NMOS Logic Design
Dynamic Response of Logic Gates
The Intel Core i7-2600 microprocessor is fabricated in a 32-nm technology. The design requires
250 million logic gates and is placed in a pac
Udo Klein
6 May 2011
1.
Digital Electronics EE094IU
Homework 8 BJT Logic Design
Emitter-Coupled Current Switch
What are the voltages at vCl and vC2 in the circuit below for vI = -1.6 V, IEE = 2.5 mA,
RC = 700 , and VREF = -2 V?. Assume F = 80 for both tra
Udo Klein
International University
Scool of Electrical Engineering
Digital Electronics EE095IU
Lab 4: MOS Logic Gates
[1] Full name:
Student ID number:
[2] Full name:
Student ID number:
[3] Full name:
Student ID number:
_
_
_
_
_
_
Class:
_
Date:
_
Page 1
Udo Klein
18 Mar 2011
1.
Digital Electronics EE094IU
Homework 5 Field-Effect Transistors
NMOS I-V Characteristics
The output characteristics for an NMOS transistor are given in the figure below.
(a) What are the values of Kn and VTN for this transistor?
(