Mallard ECE 290: Computer Engineering I - Spring 2009 - HWK #5 Solution
3/29/09 8:31 PM
HWK #5 Solution
Problem 5.1 For convenience, let's first write the functions in canonical SOP form and draw the K-maps: f(x,y,z) = AND(M1,M4,M6) = OR(m0,m2,m3,m5,m7) g
Mallard ECE 290: Computer Engineering I - Spring 2009 - HWK #2 Solutions
3/29/09 8:31 PM
HWK #2 Solutions
Problem 2.1 a . If X has no errors, it must have an even number of ones - because an even parity bit was appended when it was sent. So we need to out
Written Hwk #8 Solution
Problem 8.1 (a)(i) The following next-state table also includes the output z and the excitations T1 and T2 for use in part (ii), J1, K1 and J2, K2 for use in part (iii), and S1, R1 and S2, R2 for use in part (iv). Q1 Q2 x 0 0 0 0 1
Mallard ECE 290: Computer Engineering I - Spring 2009 - HWK #1 Solutions
3/29/09 8:32 PM
HWK #1 Solutions
SOLUTIONS Problem 1.1 Before we begin, notice that each of the 5 cards has 16 numbers, exactly one of which is a power of 2. The numbers are listed i
HWK #1 Solutions
Problem 1.1
In part (a) we can use the following weights: 1 gm, 2 gm, 4 gm, 8 gm, 16 gm, 32 gm In part (b) we can use the following weights: 1 gm, 1 gm, 3 gm, 3 gm, 9 gm, 9 gm, 27 gm, 27 gm In part (c) we can use the following weights: 1
HWK #3 Solutions
Problem 3.1 a.
b. A = d1+d0 -> A' = d1'd0' w = d3+d2(d1+d0) = d3+d2A (distributive) Similarly, x = d2A' + d2'(d1+d0) = d2A' + d2'A (= d2 XOR A) y = d1d0 + A' z = d0' c. To implement these expressions, use a total of eight 2-input NAND gat
HWK #4 Solution
Problem 4.1 (a) h(A,B,C,D)= OR(m1,m2,m6,m8,m13,m14,m15,d0,d4,d7,d10) h(A,B,C,D)= AND(M3,M5,M9,M11,M12 ,d0,d4,d7,d10) (b) There are 2 minimal SOP expressions. I shall explain first how I obtained these; their K-maps are provided below.
Look
HWK #5 Solution
Problem 5.1 For convenience throughout this problem, let's start by writing out the Kmaps: yz yz yz 00 01 11 10 00 01 11 10 00 01 11 10 0 0 0 1000 0001 0111 x x x 11 1 1 1 11 0 0 1 11 0 0 1 f g h
a. By putting x, y, and z at the inputs of
Written Hwk #7 Solution
ECE 290
Problem 7.1. (a) CD 00 01 10 11 (b) (i) Q+ Q Q 0 1 This circuit has D and D' feeding into the NAND gates, so this corresponds to having S and R never equal.
Problem Set #7
Due: October 10, 2007
(ii) CD 00 01 10 11 wxyz 11yz
ECE 290 Fall 2007 Homework 9 Solutions
9.1 a.
b.
9.2 a.1.
a.2.
a.3.
b.
Using an asynchronous clear for the circuit implementation in part 2 above would not behave correctly. As shown in the timing diagram below, as soon as the state of 18 is reached the c
Written Hwk #10 Solutions
Problem 10.1. For each instruction, we have three options: we can use FS = 0000 (F = A), 0111 (F = A), or 1100 (F = B). We will use the first for all of these; nothing besides FS changes if 0111 is used, but if 1100 is used MB mu