The Chinese University of Hong Kong Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise #4 Suggested Solution 1. (4-20) A serial two's complementer is to be designed
ERG2020A Tutorial 9
Sequential System Design Examples [Complete Version]
Timing Analysis
[CSC1410 96-97 Q7] Complete the waveform Y1 and SYNOUT for the given sequential circuit
ASYNIN S R Y1 D C SYNOU
ERG2020A Tutorial 9
Sequential System Design Examples [Questions ONLY version]
Timing Analysis
[CSC1410 96-97 Q7] Complete the waveform Y1 and SYNOUT for the given sequential circuit
ASYNIN S R Y1 D C
ERG2020A: Xilinx Foundation ISE Schematic Design Guide Author: Tang Wai Chung, Matthew Date: 26/9/2003 (Revised 2007) In this guide, the general procedure to create a project for schematic design in X
Department of Computer Science and Engineering, CUHK
ERG2020A (Fall 2007): Revision Exercise # 1 Posted: 4th Oct, 2007
1. Convert the following decimal numbers to binary: 1776, 1812, 1969, and 2000. P
The Chinese University of Hong Kong Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise # 1 Suggested Solution
1. Convert the following decimal numbers to binary: 17
The Chinese University of Hong Kong Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise # 2 Posted: 22 Oct, 2007
1. Give all the Essential Minterm, Prime Implicants
The Chinese University of Hong Kong Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise # 2 Suggested Solution
1. Give all the Essential Minterm, Prime Implicants (P
The Chinese University of Hong Kong Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise # 3
1. Determine a min. SOP expression for [5 pts] f(a,b,c,d,e) = (a+ c + d)(
The Chinese University of Hong Kong Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise # 3 Suggested Solution
1. Determine a min. SOP expression for [5 pts] f(a,b,c
The Chinese University of Hong Kong Department of Computer Science and Engineering
ERG2020A (Fall 2007): Revision Exercise # 4 1. (4-20) A serial two's complementer is to be designed. A binary integer
ERG2020A Tutorial 8
Sequential System Design
What is Sequential Circuit?
A synchronous sequential circuit is built from 2 parts:
Memory elements: store the current state of the circuit, e.g. latches
ERG2020A Tutorial 7
Quiz 2 Review Schematic Design with Xilinx (II) Nim & Lab 3
Quiz 2 Review
Q1(c): substitution technique Q2: easy Q3: Essential Implicate is a sum term. Q4: SOP, POS of f; SOP, PO
ERG2020A: Digital Logic & Systems (Fall 2007)
Quiz #1 Suggested Solution 1. Convert the following (positive numbers) numbers from the given bases to the other three bases listed in the table: (18%)
An
ERG2020A: Digital Logic & Systems (Fall 2007)
Quiz #2 Suggested Solution 1. Reduce the following Boolean functions to a minimum SOP form. (use Boolean Algebraic rules only). (a) F (W, X, Y, Z) = W X(Z
ERG2020A: Digital Logic & Systems (Fall 2007)
Quiz #3 Suggested Solution 1. Simplify the following Boolean equations using K-map method. The answer should be in (1) sum-of-products and (2) product-of-
ERG2020A: Digital Logic & Systems (Fall 2007)
Quiz #4 Suggested Solution 1. Based on the characteristic table of SR latch, we have the following excitation table: C 0 1 1 1 1 1 1 1 1 W X 0 0 0 0 1 1 1
ERG2020A (Fall 2007) Tutorial 11: Introduction to Computer Architecture
TANG Wai-Chung, Matthew
Department of Computer Science and Engineering, The Chinese University of Hong Kong
November 27, 2007
Ma
ERG2020A Tutorial 1
Course Introduction Number System Lab Introduction
Course Introduction
Lecturer: Prof. Lee Kin Hong (khlee) @ SHB 1017 Tutors:
Zhang Yubin, Robin (ybzhang) @ SHB 506 Wang Jin
ERG2020A Tutorial 3
Boolean Algebra (2) Karnaugh Map (K-map) (1)
Basic Boolean Operators
Basic gate types - AND: output is 1 if BOTH inputs are 1 ab, ab, ab - OR: output is 1 if EITHER inputs is 1
ERG2020A Tutorial 5
Advanced K-map Quine-McCluskey Method Quiz 1 Review
Slides borrowed from ERG2020B
KMap with Don't Cares
F = m(0,2,3,4,14,15) D = m(1,11,13) Don't cares can be treated as 1's or
ERG2020A Tutorial 6
Schematic Design with Xilinx Foundation 1.5i
Outline
Field Programmable Gate Array (FPGA)
What is FPGA? Why FPGA? Basic Structure of FPGA
Schematic design using Xilinx Foundation
Revised 9/2013
Page 1 of 3
GUIDELINES FOR M.S.E. DEGREE IN CIVIL ENGINEERING:
CONCENTRATION IN STRUCTURAL ENGINEERING1
General
An applicant for the M.S.E. degree must present the equivalent of an unde