Paging with TLB
Kernel needs to flush TLB at every context switch.
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for
faster access next time:
Processes use 10% of its pages 90% of the time.
When the TLB is ful
First In First Out
Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
3 frames per process.
15 page faults.
Adding more frames can cause more page faults:
Silberschatz, Galvin and Gagne 2013
Another Paging Example
Main memory size: 4GB (byte addressable):
How many bits for an address?
Page/Frame size of 4KB
How many frames?
Process size is 4MB
How many pages?
How many bits for the offset?
How many bits for the page number?