Department of Electronic Engineering
City University of Hong Kong
EE 2000 Logic Circuit Design
Laboratory Manual
Laboratory Sessions
LAB1
Design a two-digit BCD adder with Multimedia Logic
(1 week)
LAB2
Implementation and Analysis of an Arithmetic Logic U

EE 2000 Logic Circuit Design
Semester A 2014
Tutorial 7
1.
An active-LOW SR latch is shown in Fig. 1, sketch the output waveform of Q based on the
inputs as shown in Fig. 1. Assume that Q starts LOW.
Fig. 1
2.
Two edge-triggered SR flip-flops are shown in

EE 2000 Logic Circuit Design
Semester A 2014
Tutorial 10
1.
Using JK FFs and with the minimum number of states to design a counter with
counting sequence: 0,4,2,1,6 and repeat. State whether the circuit is a self started
circuit.
2.
Design a sequential ci

EE2000 Logic Circuit Design
1
EE2000 Assignment 1 (Total 40 marks)
Q1.
Perform the subtraction with the following unsigned binary numbers by taking the 2's
complement of the subtrahend and then add, in 6-bit 2s complement form. State if there is
overflow

EE 2000 Logic Circuit Design
Semester A 2014
Tutorial 9
1.
Reduce the number of states in the following state table by implication table method and
show a new state table with states elimination.
Next state
Present state
a
b
c
d
e
f
g
h
2.
x0
f
d
f
g
d
f

EE 2000 Logic Circuit Design
Semester A 2014
Tutorial 11
1.
Using a synchronous binary counters as shown in Figure 1, design and draw a counter
to generate the following repeating sequences 2 to 9 repeatedly for a free running
clock.
Syn. Binary
Counter
Q

EE 2000 Logic Circuit Design
Semester A 2014
Tutorial 8
1.
Construct a 4 x 16 decoder (with enable input) using five 2 x 4 decoder (with enable input)
modules. Show the schematic diagram neatly.
2.
How many selection lines are contained in a multiplexer w