Pre-Lab 10: An Introduction to High-Speed Addition
Celia Meza
ECEN 248 506
TA: Zhixing Li
Date: April 12, 2016
1. Code is attached
2. Code is attached
3. There are 26 gates.
4. The gate delay is GPU + BCALAU + CLU + SU = 1 + 2 + 2 + 1= 6 gate delays
16 +

Lab 5: Simple Arithmetic Logic Unit
ECEN 248
Date: October 11, 2016
Objectives:
The purpose of this lab was to apply Twos Complement arithmetic to the adder/subtractor circuit and
multiplexer properties.
Design:
The design for Lab 5 was to create an arith

Lab 6: Introduction to Logic Simulation and
Verilog
ECEN 248
Date: October 18, 2016
Objectives:
The purpose of this lab was to introduce Verilog programming, which is an alternative to breadboarding
when compiling complex circuits. Using the bit of knowle

Lab 4: Rudimentary Adder Circuits
ECEN 248
Date: October 4, 2016
Objectives:
The purpose of this lab was to introduce half-adder, full-adder, and ripple carry adder circuits, specifically a
2-bit ripple carry adder circuit, and how they all are related.
D

Pre-Lab 10
1.
`timescale 1 ns / 1 ps
`default_nettype none
/*This module describes the Carry Generate/Propagate*
*unit for 4-bit carry-lookahead addition
*/
module generate_propagate_unit(G, P, X, Y);
/*ports are wires as we will use dataflow*/
output wir

Lab 11: A Simple Digital Combination Lock
ECEN 248-515
Date: November 29, 2016
Objectives:
The purpose of this lab was to design a circuit that mimics that actions of a rotary combination lock on a
circuit board. This means the circuit will have to be abl

Lab 9: Counters, Clock Dividers, and
Debounce Circuits
ECEN 248-515
Date: November 8, 2016
Objectives:
The purpose of this lab was to learn about sequential circuits by introducing the importance of synchronous
sequential circuits and the binary counter.

Lab 7: Digital Logic Gates
ECEN 248
Date: October 25, 2016
Objectives:
This lab introduced a higher level of abstraction in Verilog HDL known as behavioral modeling. The
multiplexers from the previous lab were recreated using this. It was also used to des

Lab 10: An Introduction to High-Speed
Addition
ECEN 248-515
Date: November 15, 2016
Objectives:
The purpose of this lab was to introduce carry lookahead adders and how they are more efficient than ripple
carry adders for some high-speed circuits because t

Lab 2: Inverter Characteristics and the Ring
Oscillator
ECEN 248
Date: September 13, 2016
Objectives:
The purpose of this lab was to give an introduction to inverter voltage characteristics using a single inverter
and an odd number of inverters in a ring,

Lab 3: Logic Minimization with Karnaugh
Maps
ECEN 248
Date: September 27, 2016
Objectives:
The purpose of this lab was to introduce Karnaugh maps and logic minimization using a theoretical
calculator circuit and LEDs.
Design:
The design for Lab 3 was to u

Lab 1: Digital Logic Gates
ECEN 248
Date: September 13, 2016
Objectives:
The purpose of this lab was to give a hands-on demonstration of logic gates that weve only seen on paper
so far, along with introduction to some equipment such as the breadboard and

Lab 10: An Introduction to High-Speed Addition
Objectives:
The objective of this lab is to learn about fast-adder circuit from a carry-look ahead
addition by designing components based on dataflow and structural Verilog. Once the code is
implemented, it w

Lab 1: Digital Logic Gates
Objectives:
In this lab, I will be introduced to gate behavior and logic interpretation as well as the
basics of circuit wiring and troubleshooting. To do so, I will explore the function of
several of the basic logic gates discu

Lab 10: An Introduction to High-Speed Addition
ECEN 248 506
Date: April 19, 2016
Objectives:
The objective of this lab is to look at carry-look ahead addition for fast addition in high
speed arithmetic units through the implementation of dataflow of struc

Lab 9: Introduction to Sequential Logic
ECEN 248 506
Date: April 12, 2016
Objectives:
The objective of this lab is to reinforce my knowledge of sequential circuits by
introducing the binary counter, an important synchronous sequential circuit. Then I will

Lab 8: Introduction to
Sequential Logic
ECEN 248-511
TA: Priya Venkatas
Date: October 30, 2013
1
Objectives:
This lab is where we will learn about sequential logic circuits. This includes learning about
latches and flip-flops and adding the element of tim

Lab 11: A Simple Digital Combination Lock
Evelyn Merizalde
ECEN 248-504
TA: Prithviraj Shome
Due: April 28th, 2016
Objectives:
The objective of this lab was to design a combinational lock using behavioral Verilog to
implement it and synthesizes in Spartan

What are the main difference between EPROM AND EEPROM?
What are the main difference between EEPROM and flash memory?
A system S counts the cycles high of the most recent pulse on a single- bit input P and displays the value
on a 16-bit output D, holding t

Lab 8: Introduction to Sequential Logic
ECEN 248-515
Date: November 1, 2016
Objectives:
This lab was conducted to introduce students to the concept of sequential logic circuits and elements such
as latches and flip-flops through Verilog.
Design:
Verilog c