106
MIT International Journal of Electronics and Communication Engineering Vol. 1 No. 2 Aug 2011 pp 106-114
ISSN 2230-7672 MIT Publications
A Review of Clock Gating Techniques
Jagrit Kathuria
M. Ayoubkhan
Arti Noor
Centre for Development of Advanced
Compu

Finite State Machines
Finite State Machines (FSMs) are a useful abstraction for
sequential circuits with centralized states of operation
At each clock edge, combinational logic computes outputs and
next state as a function of inputs and present state
in

(Synchronous)
Finite State Machines
Great - Theory!
Finally!
Some ENGINEERING!
WARD &
HALSTEAD
6.004
NERD KIT
Lab 2 is due tonight
6.004 Spring 2003
2/27/03
L07 FSMs 1
Our New Machine
k
State
Registers
Current
State
Clock
Input
New
State
k
Combinational
L

MASSACHUSETTS INSTITUTE OF TECHNOLOGY
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
6.111 Introductory Digital Systems Laboratory
Fall 2009
Lecture PSet #5
Due: Tue, 09/29/09
Problem 1. (Katz, problem 8.13) A finite state machine has one input

Page 1 of 20
Memory components and finite-state machines
indicates problems that have been selected for discussion in section, time permitting.
Problem 1. Consider the following diagram of a simple sequential circuit:
The components labeled CL1 and CL2 ar

Functional Specifications
A
input A
input B
Truth tables and sum-of-products
Primitive logic gates, universal gates
Logic simplification
Karnaugh Maps, Quine-McCluskey
General implementation techniques:
muxes and look-up tables (LUTs)
B
C
Y
0
0
0
0
0
0
1