CSE 493/593 Fall 2012 QUIZ1 Solution
10/3/2012
1. a) Which device (NMOS or PMOS) conducts a good 1? Explain your answer. (20 points)
Answer:
PMOS conducts a good 1.
The reason is as followed. Here we use an inverter as an example.
W hen Vin =0 and the gat
CSE 493/593 Fall 2012 Solution 1
1. The voltage transfer characteristics for an inverter is shown in Fig. 1.
What are NML and NMH of the inverter?
Vo
3V
0V
1V
2V
3V
Vi
Fig. 1 Transfer characteristics of an inverter
Answer:
VIL=1V, VOL=0V, so NML=1V
VIH=2V
CSE 493/593 Fall 2013
Solution2
1. The gate shown in Fig.1 has the advantage of being simple and requiring
the minimum number of transistors for the function intended.
Fig.1
a. Derive the boolean expression for F. What logic function does this gate
implem
CSE 493/593 Fall 2013 Homework 5 Solution
1. Sequential Circuit Analysis [T Flip-Flop]
Derive the state table state diagram of the sequential circuit shown in figure below.
Explain the function that the circuit performs.
Solution:
We start by writing the
CSE 493/593 Fall 2013 Homework 1
Due September 18, 2013 6:30pm
1. The voltage transfer characteristics for an inverter is shown in Fig. 1. What
are NML and NMH of the inverter?
Vo
3V
0V
1V
2V
3V
Vi
Fig. 1 Transfer characteristics of an inverter
2. Sketch
CSE 493/593 Fall 2013
Solution2
1. The gate shown in Fig.1 has the advantage of being simple and requiring
the minimum number of transistors for the function intended.
Fig.1
a. Derive the boolean expression for F. What logic function does this gate
implem
CSE593
Intro to VLSI
Exam 1 Solution
Fall 2013
1. Short answer questions.
(45 pts)
a. What is the advantage of using both NMOS and PMOS transistors as part of a Transmission gate?
Answer: NMOS can conduct a good 0 and PMOS can conduct a good 1. So there i
First Name:
CSE 493/593 Fall 2014
Homework 4
Due Nov 5, 2014 6:30pm
Last Name:
Student ID:
1. You are synthesizing a chip composed of random logic with an average activity
factor of 0.1. You are using a standard cell process with an average switching
capa
CSE 493/593 Fall 2014
Homework 1
Due Oct 1, 2014 6:30pm
1. The voltage transfer characteristics for an ideal inverter is shown in Fig. 1.
What are VIL, VOL , NML, VIH, VOH and NMH of the inverter?
Fig. 1
2. Draw schematic diagrams that implement functions
CSE 493/593 Fall 2013
Solution 3
1. Sketch a 4-input NAND gate with transistor widths chosen to achieve
equal rise and fall resistance as an inverter with WN/L =1 and WP/L =2.
Answer:
2. You are synthesizing a chip composed of random logic with an average
CSE 493/593 Fall 2013 Homework 4
Due to November 13, 2013 6:30pm
1.
. Draw the transistor-level circuit diagram for F using the
logic styles Static CMOS and Dynamic CMOS.
Static CMOS
Dynamic CMOS
(and ) in DCVSL. Assume A, B and their
2. Implement
compl
CSE 493/593 Fall 2013
Solution 1
1. The voltage transfer characteristics for an inverter is shown in Fig. 1. What are NML
and NMH of the inverter?
Fig. 1 Transfer characteristics of an inverter
Answer:
VIL=1V, VOL=0V, so NML=1V
VIH=2V, VOH=3V, so NMH=1V
2
Lecture 4
CSE493/593
Static CMOS Logic
Rabaey; Vijay and Irwin
.1
CMOS Circuit Styles
Static complementary CMOS - except during switching,
output connected to either VDD or GND via a lowresistance path
high noise margins
- full rail to rail swing
- VOH an
Lecture 3 CSE493/593
Some Slides from PSU Irwin & Vijay; some from
Rabaey et. Al. book
The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration ND - electrons
are the majority carriers
Polysilicon
W
Gate
Source
Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Introduction
July 30, 2002
Eigital
DE141 Integrated
Circuits2nd
1
Introduction
What is this book all about?
Introduction to digital integrated circuits.
CSE 493/593 Fall 2012 QUIZ3 Solution
1. Increased threshold voltage results in increased/decreased delay? Explain. (10 points)
Answer:
Increased threshold voltage (Vth) results in increased delay. This is because, when Vth is increased,
at the same Vdd, t
CSE 493/593 Fall 2012 QUIZ2 Solution
1. Show using an output waveform what is rise and fall time . (15 points)
Answer:
2. In a CMOS inverter, rise time is impacted by PMOS or NMOS device? Explain why. Fall time is
impacted by PMOS or NMOS? Explain why. (2
CSE 493/593 Fall 2012 solution 3
1. Sizing a chain of buffers.
(a) In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input capacitance
Ci = 10fF), you decide to introduce a two -staged buffer as shown in Figure 1. Assume th
First Name:
CSE 493/593 Fall 2014
Homework 2 & 3
Last Name:
Student ID:
Due: Oct 22, 2014 6:30pm (Total points equal to 2 Homeworks)
1. The gate shown in Fig.2 has the advantage of being simple and requiring the minimum number of
transistors for the funct