EECE 351 Digital Systems Design
Fall 2013
Lab #3 7-Segment Display Controller
Objectives
The objectives of this lab exercise are:
1. Create a VHDL coded sequential logic controller for the 7-segment display on the
Basys2 board
2. Instantiate the controlle
Timing Delays, Glitches, and Set-Up Time
1. Draw a timing diagram for three clock cycles of the sequence generator
controller shown below assuming that AND gates and XOR gates have a delay of
2 nanoseconds and inverters (including inversion bubbles) have
Class Exercise 3 ALU
Design an ALU with two 8-bit inputs A and B, and control inputs x, y, and z. The
ALU should support the operations described in the Table.
Inputs
xyz
0 0 0 S=AB
Operation
0
0
1 S=A+B
0
1
0 S=A*2
0
1
1 S=A/2
1
0
0 S = A NAND B (bitwise
Class Exercise 2 System computes sum of positive numbers
Design a system that repeatedly computes and outputs the sum of all positive numbers
within a 512-word register file A consisting of 32-bit signed numbers.
a. Step 1 - Capture a high-level state mac
Consider an FSM with one input I and three outputs x, y, and z. xyz should always exhibit the
following sequence: 000, 001, 010, 100, repeat while I = 1. The output should change only on a
rising clock edge. Make 000 the initial state. When I = 0, the seq
Class Exercise 2 - HLSM
Use the RTL design process to create an alarm system that sets a single-bit output
alarm to 1 when the average temperature of four consecutive samples meets or
exceeds a user-defined threshold value. A 32-bit unsigned input CT indi
Datapath Components
Comparators
Equality Comparator
Magnitude Comparator
1
Comparators
N-bit equality comparator:
Outputs 1 if two N-bit numbers are equal
4-bit equality comparator with inputs A and B
a3 must equal b3, a2 = b2, a1 = b1, a0 = b0
Two bi
Datapath Components
Multipliers
1
Multiplier Array Style
4.5
Can build multiplier that mimics multiplication by hand
Notice that multiplying multiplicand by 1 is same as ANDing with 1
Consider the multiplication of 0110 by 0011:
2
Multiplier Array Style
Datapath Components
Arithmetic-Logic Unit (ALU)
1
Arithmetic-Logic Unit: ALU
4.7
ALU: Component that can perform various arithmetic
(add, subtract, increment, etc.) and logic (AND, OR, etc.)
operations, based on control inputs
2
Multifunction Calculator
Datapath Components
Shifters
Strength Reduction
Barrel Shifter
1
Shifters
Shifting useful for:
Manipulating bits
Converting serial data to parallel or
parallel to serial
Multiply/divide by 2 for each shift
(unsigned numbers only)
Shift left once is s
Datapath Components
Counters and Timers
Up/Down Counters
Counters with Parallel Load
Clock Dividers
Event Timers
1
4.9
Counters and Timers
N-bit up-counter: N-bit register
that can increment (add 1) to its
own value on each clock cycle
0
1
0
clr
cnt
Int
Datapath Components
Register Files
1
4.10
Register Files
Accessing one of
several registers is:
32
C
OK if just a few registers
Problematic when many
Ex: Earlier above-mirror
display, with 16 registers
C
8
d0d0
4x16 4
2
4
a0
d1
load reg0
load
reg0
too
Video 20
Register-Transfer Level (RTL) Design
Intro to RTL
High-Level State Machines
1
Levels of Digital Design Abstraction
RTL Design
Higher Abstraction Levels
Introduction
RegisterTransfer Level
(RTL)
Combines register and datapath
components to crea
Video 21
Register-Transfer Level (RTL) Design
RTL Design Process
1
5.3
RTL Design Process
Capture the desired behavior using a high-level state machine
Convert that behavior into a circuit
Create a datapath
Data inputs and outputs become datapath inputs
Datapath Components
Multifunction Registers
1
Multifunction Registers
Many registers require multiple functions
Load, shift, clear (load all 0s)
And retain present value, of course
Easily designed using muxes
Just connect each mux input to achieve
de
Datapath Components
Registers with Parallel Load
&
Shift Registers
1
4.2
Registers
x
b
Common widths: 8, 16, 32
Storing data into register: Loading
Opposite of storing: Reading (does not alter contents)
a
Combinational n1
logic
n0
s1
s0
N-bit register:
EE 303
Spring 2012
Test 1
Instructor: Dr. Soumekh
Date: 02/14/2012 Time: 2:00-3:20pm Room: NSC 228
Problem 1: (17/33)
We have given
-2t+2
for
-3t<-1
2t
for
-1t<1
0.5t+1
for
1t<2
2
for
2 t <3
0
x(t)=
otherwise
(1) Sketch x(t)
(7 points)
(2) Find the analyt
Creating Combinational Logic in VHDL
1
Signal Assignment Statements
The signal assignment operator is <=
Signal Assignment Statements have the form:
Target <= source expression;
The following operators are provided for the implementation of logic
funct
Introduction to VHDL
1
Hardware Description Languages
Hardware Description Languages (HDLs)
VHDL (VHSIC Hardware Description Language)
VHSIC Very High Speed Integrated Circuit
Developed by DoD in early 1980s
IEEE Standard 1076/1987 1993 2008
Verilog
Registers for Sequential Logic Design
1
Bit Storage
Sequential logic depends upon current as well as previous values of the
inputs Thus, sequential logic must have storage
The storage element of choice is the D Flip-Flop
Symbol for DFF:
D
Q
The basic o
VHDL Register Templates
1
Register Templates
(ref: Rushton section 9.4)
- Basic Register Template
process
begin
wait until rising_edge(clk);
q <= d;
end process;
- Register Template with explicit on clause
process
begin
wait on clk until rising_edge(clk);
Finite State Machine Design using VHDL
1
FSM Example: Secure Car Key
Many new car keys include
tiny computer chip
When key turned, cars computer
(under engine hood) requests
identifier from key
Key transmits identifier
Else, computer doesnt start car
Register Set/Reset
1
Flip-Flop Set and Reset Inputs
Some flip-flops have
additional reset/set inputs
Synchronous
Q
D
R
Q
Q
D
AR
Q
D
AR
AS
Q
Q
Synch. reset: Clears Q to 0 on
next clock edge
Synch. set: Sets Q to 1 on next
clock edge
Have priority over
VHDL Test Benches
1
Product Profile: Pacemaker
Pacemaker
Osc
ra
la
Inputs: s, z
Outputs: t, p
t=1, p=0
s
rv lv
Controller
sz
ResetTimer
p
t
Wait
z
s
Timer
(counts down
from 0.8s)
t=0
p=0
sz
Pace
p=1
t=0
Basic pacemaker
2
Product Profile: Pacemaker
Pacemak
Cautions When Designing FSMs
1
Common Mistakes when Capturing FSMs
Non-exclusive transitions
For a given state, no more than one
transition condition should be true
a
If a = 1 and b = 1, we cannot
determine the next state
because both transition
conditi
Video 23
Register-Transfer Level (RTL) Design
Design of Data Dominated RTL
1
Data Dominated RTL Design Example
Data dominated design: Extensive DP,
simple controller
Control dominated design: Complex
controller, simple DP
Example: Filter
Converts digi
Video 24
Register-Transfer Level (RTL) Design
Clock Frequency and Critical Path
1
5.5
Determining Clock Frequency
Designers of digital circuits
often want fastest
performance
clk
a
b
Means want high clock
frequency
Frequency limited by longest
register