EE 330 Fall 2012
Homework 9
Due Friday October 19 at the beginning of the lecture. You MUST clearly indicate
your name and SECTION on the first page of your HW. Submissions that do not
include the section WILL NOT be graded.
There is 16 problems and one e
EE330Fall2012
Homework12
Due Friday November 9 at the beginning of the lecture. You MUST clearly indicate your
name and SECTION on the first page of your HW. Submissions that do not include the
section WILL NOT be graded.
If references to a semiconductor
EE330 Spring 2014
HW9 Solutions
EE 330 - F12
HW 9 Solution
Problem 17 Extra Credit
+ 20 Points
Verilog Code 7 points
Verilog Test Bench simulation code 6 points
EE 330 - F12
HW 9 Solution
Problem 17 Extra Credit
+ 20 Points
Test Bench Waveform 7 points
NO
Spring 2012 HW 8 Solutions
Problem 1 A circuit using an SCR that is rated at current levels of 10A is shown below. Relevant
parameters from the datasheet for this device are appended at the end to this assignment. Assume the
voltage VCC is fixed at 50V an
EE 330
Homework Assignment 4
Fall 2015 (Due Friday Sept 18)
Problem 1
3.1 of Weste and Harris (WH)
Problem 2
3.2 of WH
Problem 3
If a transistor of length 20nm and width 40nm has a gate oxide thickness of 35Ao,
how many silicon dioxide molecules will be n
EE 330 Laboratory 4 From Boolean equation to Silicon
Fall 2010
Objective:
The objective of this experiment is to implement a Boolean function description in silicon, given area and pin constraints. A second object is to introduce the concept of parameteri
HW2 solution
Problem 1. Extrapolating the data from Figure 1.4, predict the transistor count of a microprocessor
in 2016.
Solution
6 to 12 billion
Problem 2. Sketch a transistor-level schematic for CMOS 4-input NOR gate.
Solution
A
B
C
D
Y
A
B
C
D
Problem
Spring 2012 HW 5 Solutions
Problem 1 Design an 8K resistor in the ON 0.5u CMOS process. Use Poly 1 for the resistor. The widthlength ratio of an imaginary box contacting on 4 sides but enclosing the resistor should have a W/L ratio
of between 1:2 and 2:1.
HW2 solution
Problem 1. Extrapolating the data from Figure 1.4, predict the transistor count of a microprocessor in 2016. Solution 6 to 12 billion Problem 2. Sketch a transistor-level schematic for CMOS 4-input NOR gate. Solution
A
B
C
D Y
A
B
C
D
Problem
EE 330 Homework Assignment 4 Spring 2012 (Due Friday Feb 3)
Problem 1 Problem 2 Problem 3 Problem 4 Problem 5
3.1 of Weste and Harris (WH) 3.2 of WH 3.5 of WH 3.7 of WH A first-order RC filter is shown. The 3dB band edge of this filter is given 1 by 3dB .
EE 330 Exam 1 Spring 2011
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _
Instructions: Students may bring 1 page of notes (front and back) to this exam. There are 8 questions and 6 problems. The points allocated to each question and each problem are as indicated. Please
EE330 Fall 2016 hw6 solutions
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Problem 12
Problem 13
Problem 14
Verilog
`timescale 1ns/1ps
module hw6(A,B,cin,s,cout);
input
Problem 1
Problem 2
Problem 3, Problem 4
Problem 5
Problem 6
(f)
(g)
(h)
(i)
Problem 8
Problem 9
Problem 10
Problem 11
Problem 12
Problem 13
Problem 14
Problem 15
Problem 16
Problem 17
Problem 18
Problem 19
Problem 20
Problem 25
Assume the 7 segment display is shown below
Problem 26
Problem 27
Each problem is 10 points.
Problem 25 weighted as two problems.
Problem 26 weighted as two problems.
Problem 27 extra credit - 10 points.
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13)
Figure 1:verilog code for the function
Figure 2:test bench
Figure 3:output
EE 330 LAB 4: FROM
BOOLEAN TO SILICON
Logan Heinen
09/22/2015
Section A
Introduction:
In this lab, we implement a Boolean function description in silicon. We are creating a Boolean
function in Layout XL just as we did in the last lab with the inverter. We
EE 330 HW11 sols, Fall 2014
Problem 1
Problem 2
Problem 3
Problem 4
Problem 5
Problem 6
Problem 7
Problem 8
Problem 9
Problem 10
Problem 11
gain 20 log(200) 46dB
Rin
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Problem 11
Problem 12
Problem 13
Problem 14
Problem 15
`timescale 1ns/1ps
module hw8(A,B,C,D,a,b,F);
input F,a,b;
output A,B,C,D;
wire A,B,C,D;
not(abar,a);
not(bbar,b);
and(A,abar,bbar,F);
EE 330 LAB #9 REPORT:
BIPOLAR DEVICES AND
APPLICATIONS
Logan Heinen
10/27/2015
Section A
Introduction:
In this lab, I will develop measurement methods for extracting device parameters of the BJT and
to investigate applications of discrete BJTs. I will mea
EE 330 LAB REPORT 5:
RESISTORS, BONDING
PADS, AND PAD FRAMES
Logan Heinen
09/28/2015
Section A
Introduction:
In this lab, I will first investigate the design and layout of resistors made of poly. After I get a
quick understanding of resistors, I will crea
EE 330 LAB REPORT 10:
THYRISTOR DEVICE
CHARACTERIZATION AND
APPLICATIONS
Logan Heinen
11/03/2015
Section A
Introduction:
In this lab, I will become more familiar with the operation of thyristors and develop methods to
measure their key parameters. The S40
EE 330 LAB REPORT 6:
MODELS FOR MOS
DEVICES
Logan Heinen
10/06/2015
Section A
Introduction:
In this lab, I am going to investigate the relationship between the square law model of a MOS
transistor and the BSIM model. I will compare these two models and sh
EE 330 LAB REPORT 7:
MOSFET DEVICE
EXPERIMENTAL
CHARACTERIZATION AND
BASIC APPLICATIONS
Logan Heinen
10/13/2015
Section A
Introduction:
In this lab, I am going to become more familiar with the operation of the MOS transistor. I will
investigate the basic