Problem 1:
Area of one transistor = 10 10 10 = 1000 2
= 3.048 108
Diameter of wafer
Area of wafer
=
Number of dies
=
Problem 2:
3.048108
Problem 3
= 7.297 1016
7.2981016 2
50001000 2
=
The cost per die
2
2
$3500
1.4591010
=
= 1.459 1010
$2.398107
Assum
EE 330
Homework 1
Spring 2016
Due Friday Jan 15
Problem 1
Assume a simple circuit requires 1,000 MOS transistors on a die and that
all transistors are minimum sized. If the transistors are fabricated in a 22nm CMOS
process (the dimensions of a minimum-siz
EE 330 Fall 2012
Homework 9
Due Friday October 19 at the beginning of the lecture. You MUST clearly indicate
your name and SECTION on the first page of your HW. Submissions that do not
include the section WILL NOT be graded.
There is 16 problems and one e
Spring 2012 HW 9 Solutions
Problem 1 Assume the capacitors are very large.
a) Draw the small signal equivalent circuit for the amplifier shown
b) Determine the quiescent value of VC and VOUT
c) Obtain the small-signal voltage gain
d) Determine the small-s
EE330Fall2012
Homework12
Due Friday November 9 at the beginning of the lecture. You MUST clearly indicate your
name and SECTION on the first page of your HW. Submissions that do not include the
section WILL NOT be graded.
If references to a semiconductor
EE 330
Homework Assignment 4
Fall 2015 (Due Friday Sept 18)
Problem 1
3.1 of Weste and Harris (WH)
Problem 2
3.2 of WH
Problem 3
If a transistor of length 20nm and width 40nm has a gate oxide thickness of 35Ao,
how many silicon dioxide molecules will be n
EE 330 Laboratory 4 From Boolean equation to Silicon
Fall 2010
Objective:
The objective of this experiment is to implement a Boolean function description in silicon, given area and pin constraints. A second object is to introduce the concept of parameteri
Spring 2012 HW 8 Solutions
Problem 1 A circuit using an SCR that is rated at current levels of 10A is shown below. Relevant
parameters from the datasheet for this device are appended at the end to this assignment. Assume the
voltage VCC is fixed at 50V an
EE330 Spring 2014
HW9 Solutions
EE 330 - F12
HW 9 Solution
Problem 17 Extra Credit
+ 20 Points
Verilog Code 7 points
Verilog Test Bench simulation code 6 points
EE 330 - F12
HW 9 Solution
Problem 17 Extra Credit
+ 20 Points
Test Bench Waveform 7 points
NO
HW2 solution
Problem 1. Extrapolating the data from Figure 1.4, predict the transistor count of a microprocessor
in 2016.
Solution
6 to 12 billion
Problem 2. Sketch a transistor-level schematic for CMOS 4-input NOR gate.
Solution
A
B
C
D
Y
A
B
C
D
Problem
Spring 2012 HW 5 Solutions
Problem 1 Design an 8K resistor in the ON 0.5u CMOS process. Use Poly 1 for the resistor. The widthlength ratio of an imaginary box contacting on 4 sides but enclosing the resistor should have a W/L ratio
of between 1:2 and 2:1.
EE 330 Homework Assignment 4 Spring 2012 (Due Friday Feb 3)
Problem 1 Problem 2 Problem 3 Problem 4 Problem 5
3.1 of Weste and Harris (WH) 3.2 of WH 3.5 of WH 3.7 of WH A first-order RC filter is shown. The 3dB band edge of this filter is given 1 by 3dB .
HW2 solution
Problem 1. Extrapolating the data from Figure 1.4, predict the transistor count of a microprocessor in 2016. Solution 6 to 12 billion Problem 2. Sketch a transistor-level schematic for CMOS 4-input NOR gate. Solution
A
B
C
D Y
A
B
C
D
Problem
EE 330 Exam 1 Spring 2011
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _
Instructions: Students may bring 1 page of notes (front and back) to this exam. There are 8 questions and 6 problems. The points allocated to each question and each problem are as indicated. Please
EE 330 Lab Report
Laboratory 3: Layout and LVS
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly build the layout of the inverter. This requires we have clear idea of the
actual structure of the circuit suc
EE 330 Lab8
Zhang Zhong
Partner Mingda Yang
Section C
10/19/2015
Introduction
For this weeks lab, we will be more familiar with the operation of MOSFET and BJT, for example,
they can be applied as voltage controlled amplifier by changing resistance, as co
EE 330 Lab Report
Laboratory 8: Thyristor Device Characterization and Applications
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly study on the characterization and basic applications for Thyristor
Device
EE 330 Lab Report
Laboratory 5: Creating banding pad
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly learnt to build the layout of resister, diode and banding pad with CAD
tools. With the components we bu
EE 330 Lab2
Zhang Zhong
Section C
9/7/2015
Introduction
For this weeks lab, I briefly tested the basic Boolean circuits by using methods that I tried. In the
first part, I learnt about digital CMOS inverters, and in addition, I established and simulated t
EE 330 Lab Report
Laboratory 6: Models for MOS Devices
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly study on the relationship between the square-law model and BSIM
model for MOSFET. We find out the par
EE 330 Lab Report
Laboratory 5: Creating banding pad
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly learnt to build the layout of resister, diode and banding pad with CAD
tools. With the components we bu
EE 330 Lab Report
Laboratory 9: Semiconductor Applications
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly study on the applications that use MOSFETs. MOSFETs are
semiconductor devices which are familiar
EE 330 Lab4
Zhang Zhong
Section C
9/20/2015
Introduction
For this weeks lab, I firstly used parameterized cells (pcells) to build the layout of inverter, and
then I created NAND schematic and used pcells to build its layout, and used three pulse voltages
EE 330 Lab6
Zhang Zhong
Section C
10/6/2015
Introduction
For this weeks lab, I figured out the relationship between the square law model and the BSIM
model of a MOS transistor.in addition, we compared these two models in their parameters and
found that th
EE 330 Lab4
Zhang Zhong
Section C
9/20/2015
Introduction
For this weeks lab, I firstly used parameterized cells (pcells) to build the layout of inverter, and
then I created NAND schematic and used pcells to build its layout, and used three pulse voltages
EE 330 Lab Report
Laboratory 4: From Boolean equation to Silicon
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we focus on building the layout of advanced Boolean function. This requires we
have clear idea of the
EE 330 Lab Report
Laboratory 3: Layout and LVS
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly build the layout of the inverter. This requires we have clear idea of the
actual structure of the circuit suc
EE 330 Lab Report
Laboratory 2: Basic Boolean Circuits
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab we mainly building, simulate and test the Basic Boolean Circuit use the Cadence
6.1 and Verilog. We first learn
EE 330 Lab Report
Laboratory 6: Models for MOS Devices
Written by: Wenbing Ma
Lab section: G
Lab Instructor: Dejmal R
Introduction
In this lab, we mainly study on the relationship between the square-law model and BSIM
model for MOSFET. We find out the par
EE 330 Lab10
Zhang Zhong
Partner Mingda Yang
Section C
11/3/2015
Introduction
In this weeks lab, we will learn the operation Thyristors device, develop methods for
measuring key parameters of Thyristors and explore basic applications for Thyristor
device.
EE 330 Lab3
Zhang Zhong
Section C
9/13/2015
Introduction
For this weeks lab, I basically got more familiar with the layout of inverter by using virtuoso.
Then, I utilized DRC tool to check whether my layout is available or not and use it to explain the
er
EE 330 Final Project
Zhang Zhong, Mingda Yang
Section C
12/17/2015
Introduction
The final project that we made is called electronic Theremin. Electronic Theremin is
an early electronic musical instrument controlled without physical contact by the
performe