From "Digital Electronics a practical approach with VHDL" by Kleitz 9th edition: problem FPGA C10-6: The VHDL program in Figure 10-42(a) is the implementation of a J-K flip-flop.
(a) Make the necessary program additions to provide active-LOW asynchronous Set and Reset inputs in both Q and not Q outputs. Save this problem as prob_c10_6.vhd. must be done in VHDL not Verilog.
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