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Testing the clocked SR Flip-Flop I'm trying to build this circuit. The 7400 NAND IC has four NAND gates so only a single IC is required to build it.

Testing the clocked SR Flip-Flop

I'm trying to build this circuit. The 7400 NAND IC has four NAND gates so only a single IC is required to build it. I need to input the values

for A (SET) and B (RESET). After that I need to describe the output conditions as Set, Reset, Prohibited, or Hold and fill in the truth table.


diagram.jpg

truth table.jpg

diagram.jpg

truth table.jpg

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