1. This circuit is a ___?
a. edge triggered device
b. level triggered device
c. positive edge triggered circuit
d. design that requires no clock
2. This flip‐flop can latch its output. Explain the concept of latching.
3. (T/F) The outputs Q and Q' should be complementary.
4. If both the A (Set) and B (Reset) inputs of the circuit shown are set high, the output is
invalid. The high on both inputs is also called a "race" condition. Can you arrive at a reason why it might
be called a "race" condition?
5. (T/F) The clocked SR flip‐flop (along with the other flip‐flops) can remember its last condition based on
6. What is the output seen on Q and Q' if 0 is applied to A (Set) and B (Reset) and a clock pulse is
7. Using a 7404 (or 7414) and a 7408, draw a circuit that could be used as an edge detector (positive or
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