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2.a) (3) How many input bits does a control unit for the single-cycle datapath require? b) (3) How many control bits does a control unit for the
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2.a) (3) How many input bits does a control unit for the single-cycle datapath require?


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b) (3) How many control bits does a control unit for the single-cycle datapath generate?




c) (3) How many input bits (notcounting the micro-program counter bits) does a control unit for the multi-cycle datapath require?




d) (3) How many control bits (notcounting the micro-program counter bits) does a control unit for the multi-cycle datapath generate?




e) (3) How many bits does the micro-program counter (μPC) for the multi-cycle datapath (without the next-state sequencer) require for our MIPS core instruction subset (Appendix D)?



f) (3) How many bits does the multi-cycle datapath control unit provide as input to the next-state sequencer (for our MIPS core instruction subset)?



g) (3) How many bits does the next-state sequencer (for our MIPS core instruction subset) provide as input to the multi-cycle datapath control unit? 

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