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é hw4.pdf EE 2310 Homework #4 — Complex Flip Flops and Sequential Logic Name CE EE Note: All CLO 's in this problem set tie to ABET program-level criterion :1. 1. (CLO 4—Seq. Logic) The FF shown is a master-slave T FF. The clock is shown below
in the timing diagram, and the T input is activated as shown. Assume that the flip-flop
is initially in the Reset state. Then plot Q and Q-Not for the number of clock pulses
shown. "ti-Not" “Q” :£Q_Not” “T” Clock 2. (CLO 4—Seq. Logic) Using two of the T F'F’s shown below, draw a modulo-3
standard binary counter. Then output count “2.” as a new clock frequency, a digital
signal with 1/3 the frequency and a duty cycle of 33167. Show the timing below.
Assume the two FF’s are reset at time I], and then the clock and counter both run
continuously. Note: The T FF is master-slave. Timing of New Clock at 1/3 f and with 33-67 Duty Cycle 3. A four-bit parallel counter (i.e., mod-16) is to be constructed, and three even
from its output. The binary numbers 7, 11, and 14 are to be decoded, ANDed
clock pulse, and transmitted to another circuit. Signals “7,” “11,” and “14” are
cycle in duration, and are true on the next high clock (thus they are true only when ”I O <

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3. A four-bit parallel counter (i.e., mod-16) is to be constructed, and three events decoded
from its output. The binary numbers 7, 11, and 14 are to be decoded, W with the
clock pulse, and transmifled to another circuit. Signals “7,” “11,” and “14” are V2 clock
cycle in duration, and are true on the next high clock (thus they are true only when
clock is at level 1). The counter is free-running, and is only cleared at start-up by a
common reset pulse tied to all the ff reset inputs. In summary: I Counter inputs are clock and reset I Counter outputs are signals “'7,” “11," and “14” I Input signals come from the left, output signals exit to the right
0 Use the T ff shown to the right, and show the timing diagram on the form below.
(Note: Supports CLO 4—Seq. Logic, and also CLO 3—Comb. Logic) 44144L44__L__'__ '5" is" '7'! '3'! '9’! m 11! 1i| 13! It! 15! i1! 2 EE 2310, Homework #4 4. Construct a modulo-6 parallel (synchronous) down-counter from the three T master-
slave FF’s shown. That is, the counter counts backwards. Assume the counter starts at
0, then goes 0-5-4-3-2-1-0 and then back to 5, counting continuously. The counter stages are x, y, and z (x = most significant digit). The T-inputs of the stages are then TX, Ty, and T1. Remember that for each ff to toggle when the clock cycles, the T input must
be “1.” Construct a timing diagram for the three outputs of the counter on the chart
below. Use the Kamaugh map method, NOT the “short-cut” method to design the
counter. Since the flip-flops are master-slave, all outputs change on the down-going or
“backside” edge of the clock. In the truth table below, x=Qx. 3:03,, and z=Qz. Note
that counts 6 & 7 are “don’t care.” (Note: Supports CLO 4—Seq. Logic, and also CLO 3—Comh. Logic)

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N
EE 2310, Homework #4
4. Construct a modulo-6 parallel (synchronous) down-counter from the three T master-
slave FF's shown. That is, the counter counts backwards. Assume the counter starts at
0, then goes 0-5-4-3-2-1-0 and then back to 5, counting continuously. The counter
stages are x, y, and z (x = most significant digit). The T-inputs of the stages are then Tx,
Ty, and Tz. Remember that for each ff to toggle when the clock cycles, the T input must
be "1." Construct a timing diagram for the three outputs of the counter on the chart
below. Use the Karnaugh map method, NOT the "short-cut" method to design the
counter. Since the flip-flops are master-slave, all outputs change on the down-going or
"backside" edge of the clock. In the truth table below, x=Qx- y=Qy, and z=Qz. Note
that counts 6 & 7 are "don't care."
(Note: Supports CLO 4-Seq. Logic, and also CLO 3-Comb. Logic)
00
01
yz
11
10
00
01 yz
11
10
00
yz
01
11
10
X
Tz
Tx
T. =
T. =
T. =
X
Y
Z
Tx
Tz
0
0
0
1
0
0
0
0
0
0
0
0
Truth Table for Determining T's
X (MSB)
Z (LSB)
Clock
2
3
5
Counter Count
(5)
(4)
(3)
(2)
(1)
(0)
(5)
Timing of Modulo-7 Counter
EE 2310, Homework #4
5. (CLO 4-Seq. Logic) A "ring counter" is a group of master-slave D flip-flops
connected in sequence output-to-input, to make a circular shift register. One or
more of the D FF's is set to one and the rest are set to 0. Since the flip-flops are
connected in a "ring," the pattern of bits continually rotates around the shift
register once the clock starts. If one stage of the shift register is arbitrarily selected
as the "output," this stage will output O's and 1's in the sequence that the 1 and 0
values pass that particular output.
If only one 1 is set into the register, then a 1 passes the chosen output only 1 clock

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% Truth Table for Determining T’s __I__.|.__|___l__l__ (5i ‘ (4?" (sf—7 {2}"— (13m (0‘)"- (5)
Timing of Modulo-‘T Counter
3 EE 2310, Homework #4 5. (CLO 4—Seq. Logic) A “ring counter” is a group of master-slave D flip-flops
connected in sequence output-to-input, to make a circular shift register. One or
more of the D FF’s is set to one and the rest are set to 0. Since the flip-flops are
connected in a “ring,” the pattern of bits continually rotates around the shift
register once the clock starts. Ifone stage of the shift register is arbitrarily selected
as the “output,” this stage will output 0‘s and 1’s in the sequence that the l and 0
values pass that particular output. Ifonly one 1 is set into the register, then a 1 passes the chosen output only 1 clock
pulse in every N pulses, N being the number of D FF’s in the ring. The ring counter
in this case creates a new clock, with a frequency of 1IN compared to the regular
clock. More complex ring counters can be constructed, however, such as the one
below. In the case shown, three D FF’s are set to 1 (it’s 2, 4 and 6), and the rest to 0
by the “Reset” pulse. However, the outputs of FF’s l and 4 are OR'ed together to /
produce a very complex output sequence. After the Reset pulse shown on the timing
diagram, the clock starts and runs continually. Show the output “1'” for the number
of clock cycles indicated below.
C1
SatIReset
Clock \ 4 EE 2310, Homework #4

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