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Computer Architecture

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Problem
Refer to figure 2 of the Single Cycle Datapath presentation (page 17 Module 6). If the instruction
being executed is a store word
Table 3: Signals
RegDst
Jump
Branch
Memread
MemWrite
MemtoReg
ALUOp(0)
ALUOp(1)
ALUSrc
Reg Write
( valid answers are 0, 1 or X)
ALU
Add resut
Add
Reg Ost
let 2
PCSro
Branch
MemRead
Instruction $1 -26]
Control
Merto Reg
ALU Op
Memifurite
ALUSro
Reginitite
Instruction (5-21]
Read
Read
PC
address
register 1
Read
Instruction 20-16]
Read
data
register 2
Zero
Instruction
(31-01
SALU ALU
Write
Registers Read
data 2
result
Address
Read
data
Instruction
register
memory
Instruction [15-11]
Vurte
Data
data
memory
x c3-
data
Instruction [15 -0]
16
32
Sign
extend
ALU
control
hstruction [5-0]
Figure 2: Single Cycle Datapath

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