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 ARM 64-bit Register File

I want to develop and simulate a simple, pipelined ARM

microprocessor.

Using Quartus II and Modelsim for development and testing this design. Processor will mostly be structural (explicit gates and Boolean equations).

 

 

Register File:

 

 You are to construct a 32 by 64 register file using Verilog.

iWithin the 32 by 64 register file is an array of 32 different 64-bit registers. These registers must be constructed from D flip-flops (positive edge-triggered). Note that for ARM, register 31 is hardwired to always output the value zero. The

           figure below shows a block diagram of a register file.

      

 

Read Register 1 and Read Register 2 select the registers whose values are output on the Read Data 1 bus and Read Data 2 bus respectively. The Write Register input bus selects the target of the write; when RegWrite is true at the rising edge of the clock, the information on the Write Data bus is written into that register.

 



// Test bench for Register file

`timescale 1ns/10ps


module regstim();                                


parameter ClockDelay = 5000;


logic       [4:0]      ReadRegister1, ReadRegister2, WriteRegister;

logic [63:0]           WriteData;

logic                                       RegWrite, clk;

logic [63:0]           ReadData1, ReadData2;


integer i;


// Your register file MUST be named "regfile".

// Also you must make sure that the port declarations

// match up with the module instance in this stimulus file.

regfile dut (.ReadData1, .ReadData2, .WriteData,

                                                                .ReadRegister1, .ReadRegister2, .WriteRegister,

                                                                .RegWrite, .clk);


// Force %t's to print in a nice format.

initial $timeformat(-9, 2, " ns", 10);


initial begin // Set up the clock

               clk <= 0;

               forever #(ClockDelay/2) clk <= ~clk;

end


initial begin

               // Try to write the value 0xA0 into register 31.

               // Register 31 should always be at the value of 0.

               RegWrite <= 5'd0;

               ReadRegister1 <= 5'd0;

               ReadRegister2 <= 5'd0;

               WriteRegister <= 5'd31;

               WriteData <= 64'h00000000000000A0;

               @(posedge clk);

               

               $display("%t Attempting overwrite of register 31, which should always be 0", $time);

               RegWrite <= 1;

               @(posedge clk);


               // Write a value into each register.

               $display("%t Writing pattern to all registers.", $time);

               for (i=0; i<31; i=i+1) begin

                               RegWrite <= 0;

                               ReadRegister1 <= i-1;

                               ReadRegister2 <= i;

                               WriteRegister <= i;

                               WriteData <= i*64'h0000010204080001;

                               @(posedge clk);

                               

                               RegWrite <= 1;

                               @(posedge clk);

               end


               // Go back and verify that the registers

               // retained the data.

               $display("%t Checking pattern.", $time);

               for (i=0; i<32; i=i+1) begin

                               RegWrite <= 0;

                               ReadRegister1 <= i-1;

                               ReadRegister2 <= i;

                               WriteRegister <= i;

                               WriteData <= i*64'h0000000000000100+i;

                               @(posedge clk);

               end

               $stop;

end

endmodule 

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