Q6 Let H bytes he the size of the standard ATM header and L bytes represent the payload size of the ATM cell. The payload size L is to be designed and optimized. Now, a key

design criterion for L is often taken from the point of view of transmission efﬁciency

and overall delay. (a) Assume that the payload of the ATM cells to be transmitted is completely ﬁlled by

information. Propose an expression for the transmission efﬁciency E of the cell in terms of H and L. (5 marks) (b) Let D represent the overall delay arising out of a multiple-hop, store and forward,

ATM circuit. Assume zero propagation delay, the transmission rate is 2 bytes per

second for each cell and is identical across each hop and the total amount of

information to be transmitted is S bytes. Determine optimal L values to minimize D

for a l-hop, 2-hop and 3-hop ATM circuit. Write down the optimal L values for S

= 20000 bytes. What relationship can be drawn between the number of hops and

the transmission eﬁciency E when D is minimized? (Note: For simplicity, assume

that L need not be an integer.) (15 marks) (c) Determine the number of hops required so that the standard ATM cell payload size

will minimize the overall delay for S = 20000 bytes. What happens if the information size drops to S = 1000 bytes or smaller? Give a reasonable conclusion

as to what should the best payload size be. (5 marks)