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It is a question about processor pipelining (MIPS processor)

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Background The execution of an instruction in a processor can be split up into a number of stages. How many stages
there are, and the purpose of each stage is different for each processor design. Hardware units are organized into stages. Execution in each stage takes exactly one clock period. Stages are separated by
pipeline registers that preserve and pass are separated by pipeline. :Tlmel: TImeZ: TImeS: TIme-Ili 'I'ImeSi 'I'ImeSi TImETE 'I'ImeBi TIrneQ'i I I I I . . . .
. . . I I I _ : ' :
lnslructlon 3 l i — l
. . . . . . Inslmction 2 ::i i : iii! ' ' ........i : a : fl
: IF Instruction Fetch — fetch instruction from memory by using the address in the PC register, store
it in the lF—ID Register, and increment PC by 4 to get the next instruction. ID Instruction Decode and Register File read — decode the instruction and reads any operands required from the register file. EXE Execution — execute the operation or calculate an address by ALU, which is the Arithmetic and Logic Unit, performs operations such as addition, subtraction, shifts left and right, etc. MEM Memory Access — perform any memory access required by the current instruction. For loads, it
would load an operand from memory. For stores, it would store an operand into memory. For all other instructions, it would do nothing. WB Write Back — write the result into a register (destination} required by some instructions.

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1. Given the signal values for Cycle 1 to Cycle 6, answer the questions (2) and (3).
Signal
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
IF-PC_IN
8
10
14
18
1C
IF-PC_OUT
10
14
18
IF-INSTRUCTION
8E040004
BE050008
00854020
01041020
0
00854822
ID-INSTRUCTION
00000000
8E040004
BE050008
00854020
01041020
00854822
ID-RS_ADD
16
16
B
ID-RT_ADD
O
5
un
ID-RD_ADD
O
0
0
2
g
ID-IMMEDIATE
0
8
16416
4128
0
18466
ID-RS
0
0
0
0
12345678
ID-RT
87654321
ID-WRITE_ADD
O
E
ID-WRITE_DATA
0
12345678
87654321
EXE-RS
0
0
0
EXE-RT
O
EXE-IMMEDIATE
O
32
32
EXE-ALU_A
0
EXE-ALU_B
0
0
0
0
EXE ALU_OUT
EXE RT_ADD
O
EXE RD_ADD
0
0
N
0
EXE_RT_RD_ADD
O
A
5
EXE ADD NEW
0
14
28
0001008C
00004090
00000014
MEM-ALU_OUT
0
0
8
MEM-LOAD_WORD
0
0
12345678
87654321
87654321
87654321
MEM-RT
O
MEM-RT_RD_ADD
5
N
WB-ALU_OUT
0
0
0
WB-LOAD_WORD
0
0
12345678
87654321
87654321
WB-WRITE_ADD
0
0
0
5
8

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2. Find all hazards within Cycle 1 to Cycle 6, and calculate their correct values. (40 marks)
Register
Instruction(s)
Correct value
e.g. )
I1 -&gt; 12
OXOECE2300
3. Identify the type(s) of all hazards happened within Cycle 1 to Cycle 6. (10 marks)
Register
Instruction(s)
Type of Hazard
[Structural / RBW / Load-use]
e.g. )
I1 -&gt; 12
Structural

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