<br/><br/>UNIVERSITYOFGHANA<br/>(Allrightsreserved)<br/>B.A/BSc.
COMPUTER SCIENCE, SECOND SEMESTER EXAMINATIONS 2019/2020
DCIT102: INTRODUCTIONTOHARDWARE ANDCIRCUIT (3 CREDITS)
INSTRUCTIONS:
Thispapercontains two Parts ( PART I and PART II)
AnswerallQuestionsfrombothPARTS
TIME ALLOWED: 48 HOURS
PARTI[ 30MARKS]
ANSWERALLQUESTIONINTHISPART
Q1.
Giventhe function F(w,x,y,z)=Σ(1,3,7,11,15)+dc(0,2,5,8)
Write the function in conjunctive normal form [3 Marks]
Minimize the function (DNF) using Karnaugh Map [7 Marks]
Construct the logic circuit diagram for the minimized function. [4 Marks] Q2.
ComputeABE16DF416 using15'scomplement [4 marks]
Computethe 36583458 in 2's complementsignedmagnitudeform.
[3Marks]

usingrules of Booleanalgebra. [4 marks]
Compute the value of 3AB16435106178 using 1's complement arithmetic leaving your final answer in Octal.[5 Marks]
PARTII[60 MARKS]
ATTEMPTALLQUESTIONS FROM THIS PART
CASE I
AziTech is one of the leading Manufacturers of modern computing systems and equipment designed for smarthomes in IoT basedenvironment. In theirrecent design of SmartController for state of the artsmarthomes, they are considering anovelCPU with 4bit data bus, memorymodule and I/O interface . The novel CPU is required to have all the functional units of a conventional microprocessor. However, the design of the ArithmeticUnitof the ALUrequires a special 4bit computation unit calledAUDiff, which wouldbeusedtopractically processall Subtraction operationusingsimpleaddition [ E.g 21 > 2 + (1)].
The Logic UnitoftheALUis requiredto operate using 2bit data bus which evaluates logical lessthan, greaterthan andequality operations on datareceived from thememory. A highspeedmemorydata busisrequiredfor data transmission between thememory andCPU & I/O. Thememorybusisrequired to transmitdata, addresses andcontrol signal between the CPU, memory and I/O with relatively low frequency with close proximity.The memoryisrequired tooperate synchronously withtheCPUclock cycle. Since theSmartControllerwouldbeusedinsmarthomes toconnectand control several devices throughsomenetwork, a highdata processingfrom thevarious devices with somesortofmemoryerrorsareanticipated.
Due the speed of the CPU, arelatively highspeedmemory withlow cost design , capable of handlingerrors isexpected withoptimaldatatransferrate.
You arerequiredto design alogical circuit that would accomplishthe task ofAUDiff. Indicate all components of logic circuitdesign necessary forthis implementation. Showappropriatetruthtables, logic equations and circuit diagrams. [20 Marks]
Design a logic circuit that would implement thetask ofthelogical unit of the ALU. Show all appropriate truth tables , logic equations and circuit diagrams. [15Marks]
Justify anddescribe themode of data transmission required to achieve high speeddatatransferbetweenthememoryandtheCPU. [4 Marks]
Justify and describe the kind of memory required to provide such an optimalperformance inthe SmartController. [6 Marks]