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<br/><br/>UNIVERSITYOFGHANA<br/>(Allrightsreserved)<br/>B.A/BSc.

COMPUTER SCIENCE, SECOND SEMESTER EXAMINATIONS 2019/2020
DCIT102: INTRODUCTIONTOHARDWARE ANDCIRCUIT (3 CREDITS)


INSTRUCTIONS:
Thispapercontains two Parts ( PART I and PART II)
AnswerallQuestionsfrombothPARTS
TIME ALLOWED: 48 HOURS
PARTI[ 30MARKS]
ANSWERALLQUESTIONINTHISPART


Q1.
Giventhe function F(w,x,y,z)=Σ(1,3,7,11,15)+dc(0,2,5,8)

-Write the function in conjunctive normal form [3 Marks]
-Minimize the function (DNF) using Karnaugh Map [7 Marks]
-Construct the logic circuit diagram for the minimized function. [4 Marks] Q2.

-Compute-ABE16-DF416 using15'scomplement [4 marks]
-Computethe 3658-3458 in 2's complementsignedmagnitudeform.
-[3Marks]
-

-usingrules of Booleanalgebra. [4 marks]
-Compute the value of 3AB16-43510-6178 using 1's complement arithmetic leaving your final answer in Octal.[5 Marks]
PARTII[60 MARKS]
ATTEMPTALLQUESTIONS FROM THIS PART


CASE I
AziTech is one of the leading Manufacturers of modern computing systems and equipment designed for smarthomes in IoT basedenvironment. In theirrecent design of SmartController for state of the artsmarthomes, they are considering anovelCPU with 4-bit data bus, memorymodule and I/O interface . The novel CPU is required to have all the functional units of a conventional microprocessor. However, the design of the ArithmeticUnitof the ALUrequires a special 4-bit computation unit calledAUDiff, which wouldbeusedtopractically processall Subtraction operationusingsimpleaddition [ E.g 2-1 -&gt; 2 + (-1)].
The Logic UnitoftheALUis requiredto operate using 2-bit data bus which evaluates logical lessthan, greaterthan andequality operations on datareceived from thememory. A highspeedmemorydata busisrequiredfor data transmission between thememory andCPU &amp; I/O. Thememorybusisrequired to transmitdata, addresses andcontrol signal between the CPU, memory and I/O with relatively low frequency with close proximity.The memoryisrequired tooperate synchronously withtheCPUclock cycle. Since theSmartControllerwouldbeusedinsmarthomes toconnectand control several devices throughsomenetwork, a highdata processingfrom thevarious devices with somesortofmemoryerrorsareanticipated.
Due the speed of the CPU, arelatively highspeedmemory withlow cost design , capable of handlingerrors isexpected withoptimaldatatransferrate.

-You arerequiredto design alogical circuit that would accomplishthe task ofAUDiff. Indicate all components of logic circuitdesign necessary forthis implementation. Showappropriatetruthtables, logic equations and circuit diagrams. [20 Marks]
-Design a logic circuit that would implement thetask ofthelogical unit of the ALU. Show all appropriate truth tables , logic equations and circuit diagrams. [15Marks]
-Justify anddescribe themode of data transmission required to achieve high speeddatatransferbetweenthememoryandtheCPU. [4 Marks]
-Justify and describe the kind of memory required to provide such an optimalperformance inthe SmartController. [6 Marks]

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