Design a digital building block adder in Verilog. Give a baseline design (of minimum cost) and an improved design (of higher performance). Compile, simulate, and synthesis your Verilog codes. Show 1. both designs are functional correct (from simulation), 2. the improved design achieves higher performance than the baseline design (from simulation), and 3. the baseline design costs less than the improved design (from synthesis). Your deliverables should include: 1. design description/specification, 2. two designs in Verilog, 3. testbenches in Verilog, 4. what software package (Verilog compiler, simulator, synthesizer), and cell library (giving cell areas, and delays) you are using, and 5. simulation and synthesis results
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