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EECE 338 - Spring 2012 Assignment 2 - Division with Sequential Control Due Date: The data provided will be the divisor and the dividend. The results...

Design a Division Unit (DIV) to be attached to a bus structure that will provide data and accept results and
other values. The data provided will be the divisor and the dividend. The results will be quotient and
remainder.
EECE 338 - Spring 2012 Assignment 2 – Division with Sequential Control Due Date: March 26, 2012 Design a Division Unit (DIV) to be attached to a bus structure that will provide data and accept results and other values. The data provided will be the divisor and the dividend. The results will be quotient and remainder. The DIV will operate on two integers, call them A and B. Thus, there are control lines writing to and reading from registers A and B. That is, the bus structure and protocol will be used to both fill and read registers A and B. When a division is requested, then another bus transaction will initiate the division, and your unit must take the two integers and calculate the equivalent of A/B. The quotient must be in a register known as the MQ register, and the remainder in a register known as the ACC register. The coding scheme for the integers is unsigned binary, and hence the algorithms that you use will not need to be capable of taking care of signed numbers. The signals utilized by this project are: Signal Activity/Action ADDR Address bus – 32 lines identifying the address DBUS Data bus – 32 bit bidirectional data transfers SYS_CLK System clock – all activity synchronous with clock SYS_RST System reset – force sanity (to idle state) REQ Request line – to request activity on bus ACK Acknowledge line – slave’s acknowledge to REQ_H READ Direction control – identifies direction of transfer The addresses of interest for this project are: Address Activity/Action 0xFFFF_1040 Read/Write A register 0xFFFF_1044 Read/Write B register 0xFFFF_1048 Do the divide 0xFFFF_104C Read the MQ register (write ignored for data) 0xFFFF_1050 Read the ACC register (write ignored for data) Your job is to design the divider. The design will be done with modules described in VHDL and combined appropriately. Your activities should include: Develop an algorithm that implements the divide, and utilize buildable constructs. Develop a data path block diagram. Again, you must use buildable constructs in the modules that you develop. Then utilizing those capabilities determine how to put together the system according to your algorithm. Identify the control points of your data path. Determine how the control points should be used to implement the algorithm on the data path. Represent this method with a state-diagram. Design a control system that operates according to your state-diagram. For this implementation, use a case construct with appropriate VHDL data types. You are to supply the following items: A brief write-up describing your device. Include any state diagrams for sequential control systems or other pertinent design information. Include an estimated time to complete the operation. Include any flow diagrams, word descriptions, or other information that you feel will help your reviewer comprehend your brilliant design. VHDL as appropriate (be sure to comment extensively). Simulations of the system (a test bench will be provided).
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